Staff Signal Integrity Engineer

Qualcomm; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks a Staff Signal Integrity Engineer to lead end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and other connectivity platforms.

The role requires strong ownership of high-speed interfaces, cross-functional leadership, and the ability to drive design convergence across silicon, packaging and board teams, delivering products that meet KPIs for performance, yield and power.

Qualifications

• 12+ years of experience in Signal Integrity / Power Integrity.
• Proven ownership of multiple tapeouts or high-volume products.
• Deep expertise in transmission line theory, EM fundamentals, and jitter/noise coupling.

Responsibilities

• Own end-to-end SI/PI closure for programs from pre-silicon to production.
• Define design targets and layout guidelines for all high-speed interfaces.
• Influence architecture decisions early in the product lifecycle.
• Lead cross-functional design reviews and sign-offs.
• Mentor engineers across SI/PI domains.

Skills

SI/PI ownership

High-speed interfaces

Signal Integrity

Cross-functional leadership

Education

Bachelor's degree in Electrical/Electronics Engineering

Master's degree in Electrical/Electronics Engineering

PhD in Electrical/Electronics Engineering

Tools

HFSS

ADS

Sigrity

CST

HSPICE

VNA

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer,

Title - Staff Signal Integrity Engineer

This role represents individual contributor within the CHS Signal Integrity organization responsible for end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, Automotive and various other connectivity platforms.

The engineer acts as

• System SI/PI owner across full platform (SoC package board connectors external systems)
• Technical owner for high-speed interfaces and system margins
• Cross-functional leader driving SIPI driven design convergence across silicon, package, and platform teams

Core Responsibilities

• Own end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)
• Define design targets and layout design guidelines for all high-speed interfaces
• Influence architecture decisions early in product lifecycle
• Ensure SI/PI alignment with product KPIs (performance, yield, power, cost)
• Drive new IP co-design across IC/IO/PHY, package, and PCB
• Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)
• Influence PDN architecture definition at system and package level, provide related optimum cost solutions
• Ensure cross functional alignments. Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem
• Lead design reviews and signoff decisions
• Represent SI/PI in program reviews and leadership forums
• Define company-wide SI/PI methodologies
• Drive correlation between pre-silicon models and silicon/lab data
• Lead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions
• Drive best practices adoption across programs
• Establish golden methods for system SI/PI
• Mentor senior engineers across SI/PI domains

High-Speed Interface Expertise

• Memory: LPDDR4/5/6
• High-speed IO: PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs
• Camera/Display: MIPI CSI/DSI
• System PDN

Required Qualifications / Experience

• 12+ years in Signal Integrity / Power Integrity / High-speed systems
• Proven ownership of multiple tapeouts or high-volume products

Domain Expertise

Deep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling. Strong hands-on experience with: Tools: HFSS, ADS, Sigrity, CST, SIwave, HSPICE; Measurement: VNA, TDR, real-time scopes

Preferred Differentiators

• Experience with: Packaging technologies like FCBGA, 2.5D/3D; Products like Data center, Compute and Servers
• Track record of Patents, standards contributions, or published work internal / external conferences

you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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