Staff - Mixed-Signal Design RTL Design Engineer

TylSemi, Inc.; Bengaluru; Hybrid; INR 4,000,000 - 6,500,000; Full time

Job summary

TYLsemi, Inc. is seeking a Staff - Mixed-Signal Design RTL Design Engineer in Bengaluru Hybrid/on-site. The role focuses on designing production-quality RTL for digital control loops and integrating 3rd party IPs to power AI/HPC devices.

You will work with analog designers on loop compensation and performance across PVT. 8+ years in power/mixed-signal design is expected. Architect digital PID/cascade control loops for IVRs operating at 10-100MHz, with strong background in MATLAB/Simulink

Qualifications

• 8+ years of relevant experience in power management ICs or high-performance mixed-signal design.
• Strong RTL background with micro-architecture and logic design knowledge.
• Proven experience translating MATLAB/Simulink control algorithms into RTL.
• Familiarity with high-frequency power converter control and digital PWM modulators.
• Experience with mixed-signal verification flows (analog-digital co-simulation).
• Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities.

Responsibilities

• Architect and implement digital PID/cascade control loops for high-frequency IVRs (10-100MHz).
• Design production-quality RTL (Verilog/SystemVerilog) for control loops and state machines.
• Integrate 3rd party IPs and collaborate with analog designers on loop compensation and delay budgeting.
• Analyze and optimize area, power, timing, and metastability across PVT corners.

Skills

RTL design

Digital control

MATLAB/Simulink

Mixed-signal design

Verification flows

Synthesis tools

Power management ICs

DPWM concepts

Education

BSEE / MSEE or PhD

Tools

Verilog/SystemVerilog

Synthesis tools

Co-simulation

Job description

Staff - Mixed-Signal Design RTL Design Engineer

About this position

About TYLsemi, Inc.

The Opportunity

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead.2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.Translation:We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.No endless meetings, no PowerPoint presentations to convince middle management.Remote-Friendly, Global TeamUS team:Bay Area preferred, but we hire the best people regardless of locationIndia team:Building a world-class design center in BangaloreMove Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We ValueOwnership mindset.You're not here to execute someone else's roadmap. You're here to define it.Bias for action.We move fast. Analysis paralysis doesn't fly here.Deep technical expertise.This is hard engineering. We need people who've shipped real silicon and debugged real hardware.Low ego, high standards.We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

The team has done this before.We've built and exited semiconductor companies at scale. This isn't our first rodeo.

The traction is de-risked.We have LOIs, strategic investors, and a clear path to revenue.

The work is consequential.You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet.Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

WhatYou’llDo

Architect , and implementdigital PID / cascade control loops(voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs operating at 10-100MHz.

Design production-quality RTL(Verilog /SystemVerilog) for control loops, state-machines and related designs.

Design and implement supporting digital blocks and integrate 3rd party micro-controller etc IPs. Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.

Analyze andoptimize forarea, power, timing, and metastability in the digital controller across PVT corners.

Support silicon bring-up, debug, and controller tuning on lab hardware.

WhatWe’reLooking For

BSEE / MSEE or PhD with8+ years of relevant experience in power management ICs or high-performance mixed-signal design. Strong RTL background: Solid understanding of micro-architecture and Logic design as well as digital control systems etc.

Proven experiencedesigning and / or converting MATLAB/Simulink control algorithms intoclean, synthesizable RTLKnowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling.

Familiarity with high-frequency power converter control and digital PWM modulators (DPWM).

Experience with mixed-signal verification flows (analog-digital co-simulation).

Good understanding of analog effectsimpactingdigital control: loop delay, sensor non-idealities, inductor non-linearities, PDNresonances.

Proficiencyin digital design tools for synthesis, simulation etc.

Good to Have

Prior experience designing digital controllers forintegrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery.

Knowledge of advanced topologies: 3-level buck, multi-level converters, hybrid switched-capacitor+ inductive converters.

Experience with formal verification or assertion-based mixed-signal verification.

Location

Hybrid / On-site – Bengaluru