Staff EDA Engineer

Lattice Semiconductor; Pune District; Presencial; INR 2 400 000 - 4 200 000; Tempo integral

Resumo da oferta

Lattice Semiconductor is seeking a Senior CAD/EDA Engineer for our Pune, India CAD/EDA group. The role focuses on STA signoff, hierarchical timing models (ETM/QTM), and physical implementation across advanced nodes, driving signoff workflows and model accuracy.

The candidate will deploy exposure to PrimeTime, Tempus, and industry variation techniques, while collaborating with global teams to optimize timing closure and PNR flows for FPGA-related designs.

Qualificações

• BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience.
• Experience on 5, 7, 16, or 28 nm process nodes.

Responsabilidades

• Own and maintain MCMM STA signoff methodology and automation.
• Develop timing signoff flows using PrimeTime, PrimeTime SI, and Cadence Tempus.
• Deploy variation modeling (AOCV/POCV/LVF) and margining across nodes.
• Drive crosstalk and signal integrity analysis and RT/RTL to signoff timing correlation.
• Define and automate SDC generation and cross-stage validation.
• Own ETM extraction for hardened blocks and QTM for non-implemented blocks.
• Develop context-aware model generation and top-level timing closure strategies.
• Provide guidance on ETM/QTM/ILM usage and document trade-offs.
• Mentor junior CAD engineers and collaborate with distributed teams.

Conhecimentos

Static Timing Analysis

Place & Route

ETM/QTM

Timing signoff

Layout signoff tools

Formação académica

BS/MS in EE/ECE/CoE

Ferramentas

Synopsys PrimeTime

Cadence Tempus

Cadence Innovus

Synopsys IC Compiler II

Cadence Fusion Compiler

Descrição da oferta de emprego

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results‑oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

Lattice is seeking a Senior CAD/EDA Engineer with deep expertise in Static Timing Analysis (STA), Place and Route (PNR), and hierarchical timing abstraction using Extracted Timing Models (ETM) and Quick Timing Models (QTM), to join our CAD/EDA Engineering group in Pune, India. Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes.

This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines.

Static Timing Analysis and Signoff

• Own and maintain the multi‑corner multi‑mode (MCMM) STA signoff methodology, including constraint development, timing closure criteria, and signoff sign‑check automation.
• Develop and support timing signoff flows using Synopsys PrimeTime, PrimeTime SI, and Cadence Tempus, covering setup, hold, recovery/removal, and transition/capacitance checks.
• Deploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes.
• Drive crosstalk and signal integrity analysis, noise‑aware timing, and correlation between implementation and signoff timing engines.
• Define and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages.

Timing Abstraction: ETM and QTM

• Own the hierarchical timing model generation methodology, including ETM extraction for hardened blocks and IP, and QTM construction for blocks that are not yet implemented.
• Define model validation and correlation procedures that quantify ETM/QTM accuracy against flat and full block timing, and establish acceptance criteria for model release.
• Develop automation for context‑aware and mode‑aware model generation, interface logic model (ILM) alternatives, and model regeneration triggered by block‑level ECOs.
• Drive top‑level timing closure strategies that rely on abstracted models to reduce runtime and memory footprint on large hierarchical designs.
• Establish guidance for design teams on when to apply ETM, QTM, ILM, or flat analysis, and document the accuracy and runtime trade‑offs of each.

Physical Implementation and Place and Route

• Develop and support physical design place and route and tape‑out flows for advanced FinFET nodes (28nm, 16nm, 7nm and below) using Cadence Innovus and/or Synopsys IC CompilerII and Fusion Compiler.
• Drive floorplanning, power planning, placement, clock tree synthesis, and routing methodology, including low‑skew and clock mesh structures.
• Own post‑CTS and post‑route tool ECO flows, timing and DRV closure automation, and physical‑aware ECO implementation.
• Support early IR drop and power analysis, EM/IR signoff hooks, and congestion and routability analysis within the implementation flow.
• Support IP block and full‑chip integration for designs on 5, 7, 16, and 28nm process nodes.

Methodology, Automation, and Support

• Create, release, and maintain design scripts and utilities that automate EDA tool flows across physical design, timing signoff, and QA.
• Define and implement comprehensive design QA procedures and regression test suites for the backend PNR and STA flows.
• Track and resolve tool and technology file issues through hands‑on, objective‑driven engagement with foundry and EDA vendor support teams.
• Drive cross‑functional initiatives and design methodology alignment across geographically distributed design and CAD/EDA teams.
• Document and deliver training on developed methodology and EDA flows to the broader engineering organization.
• Monitor EDA industry trends and new tool capabilities by attending conferences and research forums and evaluate their applicability to Lattice flows.
• Mentor junior CAD engineers and serve as an escalation point for complex timing and physical design issues.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India.

We Value Diversity

At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.

Core Values

At Lattice, our core values aren’t just something we look for in candidates – they’re something we actively cultivate and live by every day.

GROWTH

We foster a culture where everyone strives for continuous learning and development. We challenge ourselves to boldly deliver exceptional growth and value for customers and shareholders.

RELIABILITY

Our customers trust us to deliver, and we take that responsibility seriously. By committing ourselves to dependable supply, support, and solutions, we build strong collaboration that lasts and thrives.

EXECUTION

Innovation turns great ideas into results. Together, we create differentiated products and solutions through disciplined planning, decisiveness, and timely delivery with uncompromising quality.

ACCOUNTABILITY

We own our actions and outcomes: holding ourselves to the highest standards, agilely adapting to change, delivering on our commitments, and empowering each other to drive our success.

TRANSPARENCY

Openness builds trust. We lead with integrity and candor, facing hard facts and embracing tough conversations with clear communication, decisive action, and open honesty at every level.

Lattice is strengthening its leadership in compute, communications, industrial, and embedded markets – underscored by multiple award wins that recognize its innovation, leadership, workplace culture, and collaboration‑driven solutions.

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. For over 40 years, Lattice has driven innovation in the semiconductor industry. Our compact, power‑efficient field programmable gate arrays (FPGAs) are essential to building a secure, intelligent, and connected world. Lattice is the #1 supplier of small FPGAs worldwide, with the largest installed base in the industry. Our solutions are trusted by over 11,000 customers globally, spanning the compute, communications, industrial, and embedded markets. Founded in 1983 in Oregon’s Silicon Forest, Lattice has grown into a global leader with a passionate team dedicated to pushing the boundaries of programmable logic and fostering a culture of innovation. Headquartered in Portland, Oregon with major operations in San Jose, California, Shanghai, China, and Manilla, Philippines.