Staff AI Compiler Engineer

Mulya Technologies; India; On-site; INR 3,500,000 - 7,500,000; Full time

Job summary

Mulya Technologies seeks an experienced compiler leader to optimize AI model execution on graph compilers. You will architect and implement passes to improve latency and hardware utilization, collaborating with ML researchers and hardware engineers to deploy models efficiently across GPUs, TPUs, and ASICs.

Responsibilities include integrating state‑of‑the‑art compiler techniques, handling IR generation, and guiding a team of engineers toward successful project delivery in a fast‑moving

Qualifications

• Bachelor’s or Master’s degree in CS/EE; Ph.D. preferred.
• 7–10 years in compiler development with AI/ML graph focus.
• Proficiency in AI graph compiler frameworks (MLIR, Torch-FX).
• Strong background in hardware architectures and optimization (fusion, tiling).
• Familiarity with neural network operators and code generation.
• Understanding IR, parsing and semantic analysis in compiler design.
• Proficiency in C++, Python or similar languages.
• Open‑source contributions to AI frameworks are a plus.
• Experience leading and mentoring engineering teams.

Responsibilities

• Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, latency, and hardware utilization.
• Collaborate with ML researchers, hardware engineers, and software developers to design and deploy AI models, addressing hardware-specific challenges.
• Work on performance optimizations for neural network models (layer fusion, operator fusion, graph-level transformations).
• Develop compiler optimizations and passes to convert high‑level AI models into IR.
• Implement parsing, semantic analysis, and IR generation for deep learning frameworks.
• Research and integrate latest compiler/ML model optimization advances into graph compilers.
• Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.

Skills

AI graph compiler frameworks (MLIR, Py

C++

Python

Hardware architectures (GPUs/TPUs/ASIC

Code generation & IR generation

Leadership / Mentoring

Education

Bachelor’s or Master’s degree in CS/EE (Ph.D. preferred)

Job description

The 10 Hottest Semiconductor Startups Of 2025 (So Far)

Responsibilities

• Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization.
• Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges.
• Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations.
• Develop compiler optimizations and passes that convert high‑level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR).
• Implement parsing, semantic analysis, and IR generation for deep learning frameworks.
• Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers.
• Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.

Qualifications

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field (Ph.D. preferred).
• 7-10 years in compiler development, with a strong focus on AI or ML graph compilers.
• Proficiency in AI graph compiler frameworks (e.g., MLIR, Torch‑FX)
• Solid background in hardware architectures (e.g., GPUs, TPUs, ASICs) and optimization techniques such as fusion, quantization, and tiling.
• Familiarity with neural networks operators and code generation.
• Strong understanding of intermediate representations, code parsing, and semantic analysis in compiler design.
• Proficiency in C++, Python, or other programming languages commonly used in compiler development.
• Open‑source contributions to AI software frameworks and libraries is a plus
• Demonstrated experience leading and mentoring engineering teams with successful project delivery