Sr. Staff Engineer – Power Lead, Systems Architecture

Nutanix; Bengaluru; On-site; INR 550,000 - 1,200,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru is seeking a Sr. Staff Power Lead – Systems Architecture to drive system-level power design for complex SoCs and platforms, from concept to post-silicon validation.

You will define power states, DVFS policies, and cross-IP interactions, develop workload-driven models, and lead cross-functional investigations to close issues and optimize power, performance, and thermal behavior.

Qualifications

• Bachelor’s degree in Engineering, Electrical/Electronics, Computer Engineering, CS, Information Systems, or related field with 10+ years in Systems Engineering/SoC Architecture/Power Analysis; or Master’s with 8+ years; or PhD with 5+ years.

Responsibilities

• Lead system power architecture for target SoCs and platforms from concept through architecture freeze and post-silicon validation.
• Define and analyze system power states, DVFS policies, wake/sleep flows, and cross-IP power-management interactions.
• Develop workload-driven models for power and performance projection and drive cross-IP optimization.

Skills

Systems engineering

Power architecture

Analytical skills

Stakeholder leadership

Education

Bachelor's degree in Engineering/CS/related

Master's degree in related field

PhD in related field (optional)

Tools

Power-estimation tools

Trace analysis

Scripting (Python/Shell)

Job description

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Systems EngineeringGeneral Summary:We are seeking a Sr. Staff Power Lead – Systems Architecture to lead system-level power architecture, analysis, modeling, projection, optimization, and issue closure for complex SoCs and platforms. This is a systems architecture role , not a narrowly scoped circuit-power or physical-design position.The successful candidate will define and assess system power states, power islands, operating points, workload scenarios, data movement, shared-resource policies, and power-performance-thermal trade-offs. The role will establish traceability from product use cases and architecture assumptions through pre-silicon estimates, design evidence, post-silicon measurements, correlation, and next-generation improvements.Key ResponsibilitiesLead system power architecture for target SoCs and platforms from concept development through architecture freeze, design convergence, pre-silicon readiness, post-silicon characterization, and learning closure.Translate product requirements, use cases, workload behavior, concurrency, duty cycles, thermal constraints, and performance KPIs into system-level power requirements and architecture decisions.Define and analyze system power states, power islands, retention strategies, clock- and power-gating behavior, wake/sleep flows, operating points, DVFS policies, and cross-IP power-management interactions.Establish top-down system power budgets and projections and work with IP teams to decompose targets, assumptions, modes, activity profiles, and optimization requirements.Develop or guide workload-driven analytical, simulation, empirical, or hybrid models for power and performance projection.Evaluate architectural options across power, performance, thermal behavior, area, latency, responsiveness, complexity, risk, and user-experience objectives.Perform workload, use-case, concurrency, utilization, traffic, and data-movement analysis to identify system-level optimization opportunities.Drive cross-IP power optimization involving compute, memory, interconnect, multimedia, connectivity, peripherals, system infrastructure, firmware, and software policies.Track gaps between targets and projections; lead technical investigations, root-cause analysis, mitigation planning, risk assessment, and issue closure.Integrate IP-level models and implementation evidence into coherent system projections while making assumptions, model fidelity, uncertainty, and confidence ranges explicit.Define architecture validation and measurement requirements so that pre-silicon hypotheses can be verified on emulation, prototypes, boards, and production silicon.Correlate pre-silicon models and estimates with post-silicon rail, workload, telemetry, and performance measurements; explain material variances and feed calibrated models and architecture actions into subsequent products.Partner with SoC architecture, performance/modeling, IP architecture, RTL design, DV, physical design, firmware, software, thermal, validation, lab, and silicon teams.Communicate system power status, trade-offs, risks, recommendations, and closure plans to technical and program stakeholders.Develop reusable power-architecture methods, workload definitions, model standards, projection practices, dashboards, and review criteria.Minimum/Basic QualificationsBachelor’s degree in Engineering, Electrical/Electronics Engineering, Computer Engineering, Computer Science, Information Systems, or a related field and 10+ years of Systems Engineering, SoC Architecture, Power Architecture, Performance/Power Analysis, or related experience; orMaster’s degree in a related field and 8+ years of relevant experience; orPhD in a related field and 5+ years of relevant experience.Approximately 10+ years of relevant industry experience is preferred .Strong understanding of SoC and computer architecture, including compute subsystems, memory hierarchy, interconnects, system infrastructure, I/O, clock/reset, and HW/SW interaction.Experience in system power architecture, workload-based power analysis, power-performance analysis, system modeling, projection, optimization, or post-silicon power characterization.Ability to reason about dynamic and leakage power, operating modes, utilization, duty cycle, voltage/frequency operating points, concurrency, and thermal or sustained-performance effects.Demonstrated ability to lead cross-functional technical investigations and convert analysis into architecture or optimization decisions.Strong analytical, problem-solving, technical-communication, and stakeholder-leadership skills.Preferred Qualifications and Domain ExpertiseExperience defining SoC or subsystem power states, islands, low-power modes, sleep/idle behavior, wake-up paths, retention, power gating, clock gating, or DVFS.Experience with representative CPU, GPU, DSP, NPU/AI, memory, interconnect, multimedia, connectivity, peripheral, or full-platform workloads.Hands-on experience with power/performance modeling, sensitivity analysis, projection, workload characterization, trace analysis, scripting, or large-data analysis.Experience correlating architecture models and pre-silicon estimates with post-silicon measurements and driving variance root cause and model calibration.Familiarity with rail-level power measurements, silicon telemetry, performance counters, profiling, lab measurement methods, board bring-up, or system debugging.Working knowledge of RTL/gate-level power inputs, activity factors, leakage/dynamic splits, corners, implementation data, or power-estimation tools.Awareness of UPF/CPF, power-domain crossings, isolation, level shifting, retention, structural low-power verification, synthesis, timing, or physical-design power considerations.Understanding of PMICs, regulators, power rails, PDN/power-grid considerations, thermal management, and their relationship to SoC operating policy.Familiarity with Linux/Android, firmware, device drivers, system traces, power-management software, or Python/shell-based automation.Prior SoC architecture, subsystem architecture, IP microarchitecture, design, validation, or silicon-debug experience.Demonstrated technical leadership across distributed teams, including the ability to align stakeholders and influence decisions without direct authority.Minimum Qualifications:• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.ORMaster's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.ORPhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. 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