Sr Staff Engineer, Analog Design

GlobalFoundries Engineering Private Limited; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

GlobalFoundries in Bengaluru seeks an experienced Senior Analog IC Design Engineer to lead analog/mixed-signal IP design, schematic layout and verification across PVT conditions.

You will collaborate with cross-functional teams, perform transistor-level simulations using Cadence Virtuoso/Spectre, and contribute to silicon bring-up, validation, and documentation.

10–15 years of experience, strong fundamentals in noise, mismatch, stability, and parasitic-aware design are required.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering or related field.
• 10–15 years of analog or mixed-signal IC design experience.
• Solid fundamentals: device operation, biasing, gain, bandwidth, stability, noise, mismatch.

Responsibilities

• Design and verify analog/mixed-signal IP blocks at transistor level.
• Perform simulations across PVT, Monte Carlo, and corner cases.
• Collaborate with layout engineers for parasitic-aware design and performance closure.
• Support design reviews, silicon bring-up, validation, and documentation.

Skills

Analog IC design

Mixed-signal IC design

Transistor-level design

Circuit simulation

Python scripting

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

Cadence Virtuoso

Cadence Spectre

Job description

About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Key Responsibilities

• Design and develop key analog and mixed-signal IP blocks such as:
• Amplifiers (op-amps, instrumentation amps)
• Comparators
• Data converters (SAR, delta-sigma, pipeline familiarity)
• Bandgap references and regulators (LDO, DC-DC basics)
• Monitoring circuits (POR, power-good, etc.)
• Contribute to architecture discussions and design tradeoff analysis with senior team members
• Perform transistor-level schematic design, simulation, and verification using industry-standard EDA tools
• Analyze circuit performance across PVT conditions including:
• Corner simulations
• Monte Carlo mismatch analysis
• Noise and reliability considerations
• Work closely with layout engineers to ensure parasitic-aware design and performance closure
• Support and contribute to design reviews and verification planning
• Participate in silicon bring-up, validation, and debugging activities
• Collaborate across disciplines including layout, verification, and SoC integration teams
• Generate clear documentation for design specifications, simulations, and validation results

Other Responsibilities

• Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs
• Mentorship of junior design/layout engineers in design best practices and effective collaboration

Required Qualifications

• Bachelor’s or master’s degree in electrical engineering or related field
• 10-15 years of experience in analog or mixed-signal IC design.
• Solid understanding of analog design fundamentals: Device operation, biasing, gain, bandwidth Stability and compensation Noise, mismatch, and process variation
• Experience with transistor-level design and simulation in CMOS technologies
• Familiarity with industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.)
• Ability to run and analyze simulations across PVT and variability conditions
• Strong analytical and debugging skills
• Basic scripting skills (Python, MATLAB, or similar) are a plus
• Good communication and documentation skills
• Ability to work effectively in cross-functional, global teams

Preferred Qualifications

• Experience designing one or more analog blocks from spec to simulation (partial or full ownership)
• Exposure to silicon validation and lab debugging
• Familiarity with layout concepts and parasitic effects
• Experience with low-power design techniques
• Exposure to advanced nodes such as Bulk CMOS, FDSOI, or FinFET
• Experience contributing to tape out or silicon-proven designs

Benefits

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

We shape what's essential At GlobalFoundries you will find a vibrant work environment where collaboration and innovation thrive. Our diverse and global team shares a culture of respect and inclusivity, representing the best in the industry. We celebrate success together and are united by our dedication to excellence and our desire to improve and empower the world.