SoC Debug Subsystem Validation Engineer

Arm; Bengaluru; Hybrid; INR 1,200,000 - 2,400,000; Full time

Job summary

Arm Bengaluru seeks a SoC Debug Subsystem Validation Engineer to design validation strategies for CoreSight, ROM Table discovery, and JTAG/DAP based trace enablement. You will develop Python automation for trace collection, log parsing, and regression, collaborate across architecture, design, firmware, and software teams, and contribute to post-silicon validation and silicon bring-up.

The role emphasizes continuous learning, curiosity, and improving engineering workflows while applying

Qualifications

• Post-silicon validation or silicon bring-up experience.
• Strong understanding of Arm CoreSight and debug infra.
• Experience with ROM Table discovery, JTAG/TAP/DAP.
• Familiar with CoreSight trace technologies and ELA.
• Knowledge of AMBA (AXI/CHI) and system-level architecture.
• Experience building Python automation for validation and regression.
• Linux-based validation and CI/CD workflows.

Responsibilities

• Develop validation strategies, test plans, and test cases for the SoC debug subsystem.
• Validate debug infrastructure including ROM Table discovery and CoreSight components.
• Develop functional validation for trace and observability features (ETM, ETE, STM, ITM, TRBE, ELA).
• Validate trace capture, memory dumps, and log analysis workflows for post-silicon validation.
• Support silicon bring-up by enabling debug infra and firmware-assisted flows.
• Create end-to-end debug scenarios covering boot, firmware execution, interrupts, and hangs.
• Develop Python-based automation for validation, trace collection, and report generation.
• Collaborate with architecture, design, firmware, software, and platform teams to resolve silicon issues.
• Apply AI-assisted tools and modern workflows to speed up root-cause analysis.

Skills

Python

C/C++

Shell scripting

Debugging

Automation

Education

Bachelor’s or Master’s degree in Electronics/EE/CS

Tools

Arm Development Studio

DSTREAM

Lauterbach

FPGA emulation

Job description

Job Description: SoC Debug Subsystem Validation Engineer

We build the debug infrastructure that enables successful bring-up and validation of next-generation Arm-based SoCs. We’re looking for an experienced SoC Debug Subsystem Validation Engineer who enjoys solving complex hardware problems, building automation, and improving how engineers debug silicon.

You’ll work across pre-silicon and post-silicon platforms to validate CoreSight debug capabilities, enable silicon bring-up, and develop tools that help engineering teams diagnose and resolve challenging system-level issues.

We value curiosity, collaboration, continuous learning, and engineers who enjoy improving both products and engineering workflows.

Key Responsibilities

• Develop and build validation strategies, test plans, and test cases for the SoC debug subsystem.
• Validate the SoC debug infrastructure, including debug access, discovery mechanisms, and trace enablement (for example, ROM Table discovery, JTAG/DAP, and CoreSight debug components).
• Develop and complete functional validation for hardware trace and observability features. Examples include ETM, ETE, STM, ITM, TRBE, and ELA.
• Validate debug data capture and failure analysis mechanisms, including trace capture, scan dump, memory dump, and related debug workflows for post-silicon validation.
• Support silicon bring-up by enabling debug infrastructure and validating firmware-assisted debug flows.
• Develop end-to-end debug scenarios covering boot flows, firmware execution, memory accesses, interrupts, exceptions, and system hang analysis.
• Perform root-cause analysis by correlating traces, firmware logs, register dumps, scan dumps, and memory dumps.
• Develop Python-based automation and reusable tools for validation, trace collection, dump analysis, log parsing, regression execution, and report generation.
• Collaborate with architecture, design, firmware, software, and platform teams to resolve complex silicon issues.
• Apply AI-assisted tools, Python automation, and modern engineering workflows to improve efficiency, accelerate root-cause analysis, and reduce manual effort in day-to-day activities.

Required Qualifications

• Experience in post-silicon validation, silicon bring-up, firmware validation, or SoC debug.
• Strong understanding of Arm CoreSight architecture and debug infrastructure.
• Hands-on experience with ROM Table discovery, JTAG/TAP/DAP, MEM-AP, and debug access mechanisms.
• Experience with CoreSight trace technologies, Embedded Logic Analyzer (ELA), scan dumps, and memory dump analysis.
• Understanding of SoC boot flows, firmware initialization, clocking, reset, and power management.
• Good understanding of AMBA protocols (AXI/CHI) and system-level architecture.
• Strong Python programming skills with experience developing automation frameworks, debug utilities, engineering tools, or data-processing applications.
• Solid understanding of C/C++, Shell scripting, or Perl.
• Excellent analytical, debugging, communication, and problem-solving skills.
• Experience with Arm Development Studio, DSTREAM, Lauterbach, or equivalent debug tools.
• Experience with FPGA prototypes, emulation platforms, or simulation environments.
• Experience developing trace decoding, dump analysis, and log analysis tools.
• Experience building Python automation frameworks for validation and regression.
• Familiarity with Linux-based validation, bare-metal firmware, and CI/CD workflows.

Technical Skills

Debug Architecture: Arm CoreSight, ROM Tables, JTAG, TAP, DAP, MEM-AP, APB-AP

Trace & Debug: ETM, ETE, STM, ITM, TRBE, ELA, Scan Dump, Memory Dump

Validation: Post-Silicon Validation, Silicon Bring-up, Platform Validation, Firmware Validation

Programming & Automation: Python, C/C++, Shell

Interconnect Knowledge: AMBA AXI, CHI, Cache Coherency

Platforms & Tools: Simulation, Emulation, FPGA, Bare-Metal Silicon, Linux, Arm Development Studio, DSTREAM, Lauterbach

Education

Bachelor’s or Master’s degree or equivalent experience in Electronics Engineering, Electrical Engineering, Computer Engineering, Embedded Systems, VLSI, Computer Science, or a related field.

Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset

Accommodations at Arm

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [e-mail] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Hybrid Working at Arm

Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.

Equal Opportunities at Arm

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.