Senior Verification Engineer - ARM Fabric Unit Level

NVIDIA Gruppe; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NVIDIA Gruppe in Bengaluru is seeking a skilled Verification Engineer to lead unit-level verification for HSIO IP in Tegra chips. You will develop UVM-based test benches and define comprehensive test plans to ensure the robustness of our sophisticated hardware solutions.

The ideal candidate will hold a B.Tech or M.Tech in ECE, EE, or CSE, and possess at least four years of relevant experience with ARM architecture and verification methodologies. NVIDIA offers competitive salaries and a full range of benefits.

Qualifications

• Four or more years of experience in verification closure of complex units or SOC-level projects.
• Hands-on experience with industry-standard verification tools for simulation and debugging.

Responsibilities

• Architect test benches and craft verification environments using SV and UVM methodology.
• Define test plans and verification infrastructure for modules, clusters, and systems.
• Collaborate with architects, designers, and teams to ensure unit robustness.

Skills

Verification closure of complex units

ARM architecture and protocols (AXI, AHB, APB)

SV and UVM verification methodologies

Debugging and analytical skills

Interpersonal and communication skills

Education

B.Tech or M.Tech in ECE, EE, CSE

Job description

NVIDIA’s automotive verification group is searching for a verification engineer to lead unit‑level verification for HSIO IP. You will develop UVM-based test benches to validate in‑house ARM‑based distributed fabrics that transport control, sidebands and data across high‑performance CPU and memory subsystems, NOC‑based interconnects, and high‑speed I/Os in our Tegra chips.

What you’ll be doing

During the course of a project, you will drive the following aspects of verification for your unit:

• Architect test benches and craft verification environments using SV and UVM methodology.
• Define test plans, tests, and verification infrastructure for modules, clusters, and systems.
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards.
• Implement functional coverage and coordinate the verification closure process for the unit.
• Collaborate with architects, designers, FPGA and post‑silicon teams to ensure unit robustness.

What we need to see

• B.Tech or M.Tech in ECE, EE, CSE, or an equivalent degree.
• Four or more years of experience in verification closure of complex units, subsystems, or SOC‑level projects.
• Proven experience with ARM architecture and protocols (AXI, AHB, APB).
• Hands‑on experience with SV and UVM verification methodologies.
• Strong debugging and analytical skills; exposure to industry‑standard verification tools for simulation and debugging.
• Excellent interpersonal and communication skills, with the ability to work collaboratively in global, matrix organizations.

Ways to stand out from the crowd

• Experience using AI tools such as Claude or Cursor for code development.
• A mindset focused on continuous improvement and automation.
• Exposure to formal verification.

We are an equal‑opportunity employer and value diversity at NVIDIA. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Reasonable accommodations will be provided for individuals with disabilities.

NVIDIA offers highly competitive salaries and a comprehensive benefits package. Learn more at www.nvidiabenefits.com/.