Senior System Integration and Validation Engineer

NVIDIA AI; Bengaluru; On-site; INR 3,000,000 - 5,400,000; Full time

Benefits offered by this job

Competitive benefits

Flexible time off

Continuous learning

Job summary

NVIDIA—The Silicon Co-Design Group seeks an experienced validation engineer to own end-to-end system validation for GPU, SoC, and platform programs. You will lead cross-stack debugging, develop automated test plans, and design AI-powered workflows to accelerate validation before silicon goes to production.

Applicants should have 6+ years in post-silicon validation and demonstrateAbility to drive multi-team crisis resolution with productized fixes, while partnering with global teams across

Qualifications

• 6+ years of post-silicon validation, system integration, or platform debugging on shipped GPU, CPU, or SoC products.
• Hands-on debugging across silicon, board, and software boundaries with strong EE fundamentals in SI/PI, power, and thermal.
• Proven track record in taking ambiguous multi-team failures to root-cause closure with productized fixes.
• Demonstrated AI-driven validation workflow with measurable impact on debug velocity, coverage, or escapes.

Responsibilities

• Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale.
• Lead debug of cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — drive root cause with fixes.
• Develop test plans, scripts, and automation for next-generation chips ahead of physical builds.
• Design and deploy AI-enabled debug and validation workflows with guardrails and measurable impact on cycle time.
• Translate complex silicon and system risk into decision-ready options for technical and executive audiences.
• Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering.
• Lead crisis-mode debug task forces when programs are stuck and convert learnings into reusable methodology.
• Find critical silicon and platform issues before customers reach them by shifting validation coverage left.
• Build AI-enabled validation as a real capability with guardrails that gate production decisions.

Skills

System validation

Debug depth

GPU/SoC architecture

PVT & signal integrity

AI-driven validation

Cross-team leadership

Education

BTech/BE or MTech/ME in Electronics/Electrical/Computer Engineering

Job description

Job Requisition ID JR2024494
Job Category Engineering
Time Type Full time

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.

What You’ll Be Doing

• Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.
• Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.
• Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.
• Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.
• Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.
• Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.
• Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.
• Find critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.
• Build AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.

What We Need To See

• BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), and 6+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
• Hands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.
• At least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.
• Demonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can describe the guardrails you put in place and where AI is dangerous in your workflow.

Ways To Stand Out From The Crowd

• A history of building reusable validation methodology, debug playbooks, or test frameworks that were adopted by other programs or teams — backed by patents, conference papers, invited talks, or recognized contributions.
• Hands-on subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging — failure modes, debug instrumentation, and the tradeoffs that show up in production.
• Experience partnering deeply with a counterpart team in India or another major engineering hub — examples of shared culture, shared metrics, and shared on-call across geographies.
• AI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, regression bucketing, or automated triage deployed at team scope with adoption metrics.

NVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work.