Senior Staff Physical Design Architect (Flow & ML Automation)

SiFive; Bengaluru; On-site; INR 7,000,000 - 10,000,000; Full time

Job summary

SiFive seeks an RTL-to-GDS Flow Lead to architect the physical implementation backbone for next-gen CPU cores. The role focuses on automated, ML-driven methodologies to push PPA beyond industry standards on N3/N2 process nodes, bridging architectural intent with physical reality for predictable execution.

You will lead methodology, optimize design space with AI/ML tools, and collaborate with Synopsys to co-optimize libraries while defining floorplanning and scalable build systems for push-button

Qualifications

• 10+ years of experience in Physical Design with proven track record in high-speed CPUs (3GHz+).
• Hands-on experience with advanced nodes, especially TSMC N3; N2 exposure is preferred.

Responsibilities

• Architect, validate, and deploy RTL-to-GDS recipes for high-frequency CPU implementation.
• Lead AI/ML optimization efforts using tools like Synopsys DSO.ai to explore PPA design space.
• Interface with EDA partners (Synopsys) to influence tool roadmaps and co-optimize libraries for PPA.
• Define global floor planning, budgeting, and integration strategies for large-scale designs.
• Develop automated build systems, dashboards, and checklists to ensure predictable execution.

Skills

Physical Design

Timing Closure

Electromigration

Crosstalk Mitigation

ML-based design space optimization

Python/Tcl/Perl scripting

Education

Bachelor's or Master's in EEE, ECE, CS, VLSI, or PhD

Tools

Fusion Design Platform (Fusion Compiler, IC Compiler II, PrimeTime)

Synopsys DSO.ai

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Overview

As the RTL-to-GDS Flow Lead, you will be the primary architect of the physical implementation backbone for our next-generation, high-speed CPU cores. This is a high-visibility role focused on pioneering automated, ML-driven methodologies that push Power, Performance, and Area (PPA) beyond industry standards on N3 and N2 process nodes. You will bridge the gap between architectural intent and physical reality, ensuring predictable, world-class execution.

Key Responsibilities

Methodology Leadership: Architect, validate, and deploy “Best-of-Class” RTL-to-GDS recipes tailored for high-frequency CPU implementation.

• ML-Driven Optimization: Lead the integration and scaling of AI/ML optimization tools (e.g., Synopsys DSO.ai) to autonomously navigate the massive PPA design space.

• Strategic EDA Engagement: Serve as the primary technical interface with EDA partners (Synopsys) and IP providers to influence tool roadmaps and co-optimize Standard Cell/SRAM libraries for PPA.

• Hierarchical Strategy: Define the global floor planning, budgeting, and integration strategies for multi-million gate, high-speed hierarchical designs.

• Predictability & Scale: Design and maintain robust build systems, automated dashboards, and execution checklists to ensure “push-button” predictability and minimize manual intervention.

• PPA Modeling: Early-stage PPA estimation and pathfinding to influence RTL and architectural trade-offs.

Requirements

• Expertise: 10+ years of experience in Physical Design with a proven track record of closing high-speed CPUs (3GHz+).

• Education Qualification: A bachelor’s or master’s in E&E, ECE, CS, VLSI, or PhD is required.

• Advanced Nodes: Deep, hands-on experience with TSMC N3 is required; exposure to N2 is highly preferred.

• Tool Mastery: Power-user knowledge of the Synopsys Fusion Design Platform (Fusion Compiler, IC Compiler II, PrimeTime).

• AI/ML Integration: Demonstrated experience deploying ML-based design space optimization tools in a production environment.

• Systemic Automation: Expert-level proficiency in Python, Tcl, or Perl, with a mindset for building scalable, maintainable “Flows-as-Code.”

• Analytical Depth: Deep understanding of timing closure, IR drop, electromigration (EM), and crosstalk challenges unique to high-performance cores.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.