Senior Staff Engineer - SRAM

Synopsys, Inc.; Dadri; On-site; INR 3,500,000 - 5,200,000; Full time

Benefits offered by this job

Health benefits

Total rewards

Wellness perks

Job summary

Synopsys, Inc. in India seeks a Senior Staff Memory Design Engineer to lead SRAM bitcell and peripheral circuit design for advanced FinFET nodes. You will drive HSPICE/PrimeSim simulations, reliability analyses, and contribute to memory compiler improvements.

You will collaborate with layout and validation teams, mentor junior engineers, and help shape memory IP architectures powering AI accelerators and mobile/SoCs.

Qualifications

• 10+ years of hands-on SRAM memory design experience in production environments.
• Deep expertise in SRAM bitcell design, peripheral circuits and memory architecture.
• Proficiency with Synopsys tools including HSPICE/PrimeSim, Custom Compiler, StarRC, IC Validator and PrimeTime.

Responsibilities

• Design and optimize SRAM bitcells and peripheral circuits for advanced FinFET nodes (7nm, 5nm, 3nm).
• Run transistor-level simulations, Monte Carlo and reliability analyses across PVT corners.
• Develop and enhance memory compiler capabilities and automation flows.
• Collaborate with layout teams on cell design and parasitic closure to hit timing targets.
• Support silicon bring-up and debug, and mentor junior engineers.

Skills

SRAM bitcell design

Memory compiler

HSPICE/PrimeSim

Monte Carlo analysis

Python/Perl/TCL scripting

Layout collaboration

Education

Bachelor's or Master's in Electrical Engineering or related

Tools

HSPICE/PrimeSim

Custom Compiler

StarRC

IC Validator

PrimeTime

Job description

Senior Staff Memory Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building memory circuits that do not just pass simulation, they survive silicon. You know that an SRAM bitcell is not just six transistors, it is a balancing act between read stability, write margin, leakage, and yield, and you have made those tradeoffs enough times to know which corners will bite you at 0.6V and which ones only look scary in Monte Carlo.

When a sense amplifier fails timing at the worst-case corner, you do not panic, you pull up HSPICE, trace the critical path, and figure out whether it is a device issue, a layout parasitics problem, or a floorplan decision someone made two months ago. You have debugged silicon that came back wrong and figured out what the test data was actually telling you, not what you hoped it was saying.

You are comfortable sitting with a layout engineer to optimize a bitcell for another 2% density without breaking read margin, and you can explain to a product manager why that extra 50mV of assist voltage matters for their automotive customer. At Synopsys, you will work on SRAM IP that powers AI accelerators, mobile SoCs, and networking chips used across the industry.

What You'll Be Doing

• Design and optimize SRAM bitcells and peripheral circuits including sense amplifiers, write drivers, precharge circuits, row and column decoders, and read/write assist blocks for advanced FinFET nodes (7nm, 5nm, 3nm)
• Drive transistor-level circuit simulations using HSPICE and PrimeSim, running Monte Carlo, variability, SNM, and reliability analysis across PVT corners to ensure design closure
• Develop and enhance SRAM compiler capabilities, building automated memory generation flows that balance power, performance, area, and yield
• Collaborate with layout teams on custom cell design and parasitic closure, working through LVS, DRC, and PEX iterations to hit timing and power targets
• Support silicon bring-up and debug, correlating lab measurements with simulation models and identifying root causes when characterization data does not match expectations
• Automate design and validation workflows using Python, Perl, TCL, and shell scripting to improve efficiency and repeatability across memory development projects
• Mentor junior engineers on circuit design techniques, simulation methodologies, and design-for-manufacturing principles

The Impact You Will Have

• Your SRAM designs will be integrated into AI, HPC, mobile, networking, and automotive SoCs used by customers worldwide, directly affecting performance and power efficiency of next‑generation chips
• The memory compilers you develop will enable faster time-to-market for Synopsys IP customers, giving them flexible, high‑quality SRAM solutions across multiple process nodes
• Your circuit optimizations will push the boundaries of memory density, speed, and low‑power operation in advanced FinFET technologies
• The design methodologies and automation scripts you build will be reused across future memory IP projects, improving team productivity and design quality
• Your silicon debug work will close the loop between design intent and real‑world performance, improving correlation models and making future designs more predictable
• The technical leadership you provide will raise the bar for circuit design excellence within the memory IP team
• Your contributions to technical reviews and design discussions will shape architecture decisions that affect product roadmaps and customer engagements

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI Design, Microelectronics, or related field
• 10+ years of hands‑on experience designing SRAM memory circuits and custom analog/mixed‑signal blocks in production environments
• Deep expertise in SRAM bitcell design, peripheral circuits (sense amps, write drivers, decoders, assist circuits), and memory architecture
• Strong proficiency with Synopsys tools including HSPICE/PrimeSim, Custom Compiler, StarRC, IC Validator, and PrimeTime
• Solid understanding of CMOS device physics, FinFET technology, and design challenges in advanced nodes (16nm/7nm/5nm/3nm)
• Experience with Monte Carlo analysis, PVT validation, SNM analysis, and reliability simulations to ensure robust designs across corners
• Scripting skills in Python, Perl, TCL, or shell for design automation and flow development; experience developing SRAM compilers or memory generators is a strong plus

Who You Are

• You can look at a failing Monte Carlo run and quickly isolate whether it is a statistical outlier, a corner case that needs circuit tuning, or a fundamental architecture problem that requires a different approach
• When layout parasitics break your timing budget, you work directly with the layout team to understand the routing bottleneck and propose circuit or floorplan changes that actually solve it
• You know how to explain a complex circuit tradeoff to a product architect in two sentences without losing the technical nuance, and you can defend your design choices with data
• You do not wait for perfect specs, you ask the right questions early, align with cross‑functional teams on priorities, and make progress even when requirements are still evolving
• You have debugged silicon that did not behave as expected and worked backward from lab data to figure out what the design missed, what the model missed, or what the test setup missed
• You take ownership of your designs from schematic through silicon validation, and you care about whether they actually work in production, not just in simulation

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.