Senior Staff Engineer, Physical Verification

Renesas Electronics; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

Renesas Electronics in Bengaluru, India invites an experienced Senior Staff Engineer to drive signoff verification for advanced ASIC/SoC designs. You will own block- and chip-level PV signoff, debug violations, and ensure tapeout readiness with foundry flows.

You should bring 10–15 years in PV/PD/backend, strong Calibre/PDK knowledge, and scripting skills to maintain rule decks and support multi-team collaboration for successful tapeouts in cutting-edge nodes.

Qualifications

• Bachelor's or Master's degree in Electronics or Electrical Engineering.
• 10–15 years in Physical Verification, Physical Design, or Backend.
• Strong expertise in DRC, LVS, ERC, Antenna, Density checks.

Responsibilities

• Perform and drive signoff Physical Verification for block- and chip-level designs.
• Execute and analyze DRC, LVS, ERC, Antenna, and Density checks.
• Debug verification violations and provide actionable recommendations.
• Drive closure of signoff issues through tracking, prioritization, and cross-functional collaboration.
• Maintain and support foundry-qualified rule decks, runsets, and waiver management processes.
• Coordinate verification re-runs following design changes and ECOs to identify regressions and maintain signoff quality.
• Generate periodic signoff status reports, metrics, and violation summaries for project reviews.
• Prepare final signoff evidence including DRC/LVS-clean reports, waiver summaries, and residual risk assessments for tapeout reviews.

Skills

DRC/LVS/ERC

Calibre/PEGASUS

GDSII/OASIS

Scripting (Python/Tcl)

Foundry signoff requirements

Education

Bachelor's or Master's in Electronics/Electrical Engineering

Tools

Calibre

Pegasus

Job description

Senior Staff Engineer, Physical Verification

• Full-time


• Employment Type: Regular (PERM)


• Remote Work Available: No

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world calculates, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking an experienced Physical Verification (PV) Engineer to drive signoff verification and tapeout readiness for advanced ASIC/SoC designs. The candidate will be responsible for executing and debugging physical verification checks, driving violation closure, maintaining foundry-qualified verification flows, and ensuring block and full-chip layouts meet manufacturing requirements before tapeout.

Key Responsibilities

• Perform and drive signoff Physical Verification for block- and chip-level designs.


• Execute and analyze DRC, LVS, ERC, Antenna, and Density checks using industry-standard signoff tools.


• Debug verification violations and provide actionable recommendations to Physical Design and Layout teams.


• Drive closure of signoff issues through effective tracking, prioritization, and cross-functional collaboration.


• Maintain and support foundry-qualified rule decks, runsets, and waiver management processes.


• Manage waiver tracking and ensure compliance with foundry guidelines and project signoff requirements.


• Coordinate verification re-runs following design changes and ECOs to identify regressions and maintain signoff quality.


• Work closely with Physical Design, Layout, Foundry/PDK, and Program teams to achieve tapeout milestones.


• Generate periodic signoff status reports, metrics, and violation summaries for project reviews.


• Prepare final signoff evidence including DRC/LVS-clean reports, waiver summaries, and residual risk assessments for tapeout reviews.

Key Qualifications

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.


• 10-15 years of experience in Physical Verification, Physical Design, or Backend Implementation.


• Strong expertise in DRC, LVS, ERC, Antenna, and Density verification methodologies.


• Hands‑on experience with Calibre, Pegasus, or equivalent physical verification tools.


• Good understanding of foundry signoff requirements, PDKs, and semiconductor manufacturing rules.


• Experience in debugging and resolving complex signoff violations at block and full‑chip levels.


• Familiarity with GDSII/OASIS databases, netlists, and tapeout processes.


• Proficiency in Tcl, Python, Perl, or Shell scripting.

Preferred Qualifications

• Experience with advanced technology nodes (7nm, 5nm, 3nm, and below).


• Knowledge of Physical Design, PDN, STA, and implementation flows.


• Experience supporting multiple successful SoC tapeouts.


• Strong problem‑solving, communication, and stakeholder management skills.

Why Join Us?

Join a high-impact team responsible for ensuring silicon manufacturability and signoff quality for next-generation SoCs. You will work closely with design, implementation, and foundry teams to drive successful tapeouts on cutting-edge process technologies.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

Benefits

• We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read ourDiversity & Inclusion Statement .