Senior Staff Digital Methodology Engineer - Design for Testability (DFT)

Synopsys; Bengaluru; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

Synopsys, Inc. in Bengaluru seeks a senior DFT architect to define and drive methodologies for next-gen ASIC/SoC test solutions.

You will translate architecture decisions into deployable best practices and lead deployment of IEEE 1149.1/1149.6/1687/1500, IJTAG, and related standards across multi-billion gate designs. You will collaborate with R&D, product engineering, and strategic accounts, developing automation frameworks using Tcl, Python, and Perl to accelerate adoption and signoff, while

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
• 10+ years in semiconductor/EDA with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.
• Proven track record architecting and implementing DFT solutions for large-scale ASIC/SoC designs, including tapeouts.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments.
• Deep knowledge of scan insertion, scan compression, hierarchical DFT, ATPG/diagnosis, fault models, and coverage optimization.
• Experience deploying IEEE 1149.1/1149.6/1687/1500 in complex test access architectures.
• Proficiency with Tcl, Python, Perl, or Shell scripting for automation and deployment.

Responsibilities

• Define and drive DFT methodologies for next-gen ASIC/SoC designs across strategic programs.
• Lead deployment of scan compression, hierarchical DFT, IJTAG instrumentation, and embedded test IP.
• Architect scalable test access infrastructures using IEEE standards for multi-die systems.
• Develop automation frameworks and reusable methodology packages to accelerate adoption.
• Serve as technical leader for Synopsys TestMAX DFT/ATPG in customer engagements.
• Collaborate with R&D to influence TestMAX roadmap based on deployment challenges.

Skills

DFT architecture

ATPG

Manufacturing test

IEEE 1149.1

IEEE 1149.6

IEEE 1687

IEEE 1500

Tcl Python Perl

RTL-to-GDSII

Education

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field

Tools

Synopsys TestMAX DFT

Synopsys TestMAX ATPG

JTAG

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over a decade architecting test solutions for chips that power everything from autonomous vehicles to data centers, and you understand that DFT is not an afterthought, it is the difference between a design that ships on time and one that bleeds money in yield loss. You know the nuances of scan compression versus hierarchical DFT, not from a textbook, but from making the call on a 10-billion-gate SoC where the wrong decision costs months.

You are the person design teams call when ATPG coverage is stuck at 97% and manufacturing is demanding 99.5%. You have debugged IJTAG networks that span multiple chiplets, written the Tcl that automated what used to take three engineers a week, and sat in rooms with VPs explaining why their test access strategy needs to change before tapeout. You do not just know the IEEE standards, you have deployed them in production silicon and lived with the consequences.

At Synopsys, you will work on methodologies that define how the world's most complex chips get tested. The problems are hard, the customers are sophisticated, and what you build will matter.

What You'll Be Doing

• Define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs, translating architecture decisions into deployable best practices
• Lead deployment of advanced test solutions including scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation networks, and embedded test IP across multi-billion-gate designs
• Architect scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards for complex multi-die and chiplet-based systems
• Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl that accelerate adoption across business units
• Serve as technical leader and subject matter expert for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements and internal escalations
• Collaborate directly with R&D teams to influence TestMAX product roadmap based on real deployment challenges and customer requirements
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex DFT architecture decisions that impact tapeout schedules and silicon success

The Impact You Will Have

• Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs in AI, automotive, and hyperscale computing
• Drive measurable improvements in test coverage, pattern count reduction, and manufacturing yield through methodology standardization and best-practice development
• Influence next-generation TestMAX capabilities by translating customer deployment challenges into product requirements that shape future releases
• Accelerate adoption of standards-based test architectures across strategic accounts, reducing time-to-market and improving silicon reliability
• Improve engineering productivity across multiple programs through automation frameworks and reusable methodology packages that eliminate redundant work
• Establish Synopsys as the trusted technical advisor in DFT and manufacturing test, strengthening customer relationships and competitive positioning
• Contribute to breakthrough technologies powering autonomous vehicles, AI accelerators, and next-generation networking infrastructure

What You'll Need

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
• 10+ years in semiconductor or EDA industry with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies
• Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including successful tapeouts
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions in production design environments
• Deep technical knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, stuck-at/transition/path-delay/bridge/cell-aware fault models, and coverage optimization techniques
• Expertise deploying IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), and IEEE 1500 standards in complex test access architectures
• Experience integrating DFT IP including Codec/embedded compression, OCC, LBIST, TAP controllers, JTAG and IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers
• Strong understanding of RTL-to-GDSII flows and how DFT interacts with synthesis, physical design, timing closure, and signoff
• Proficiency with Tcl, Python, Perl, or Shell scripting for methodology automation and deployment
• Experience defining enterprise-wide DFT standards and signoff methodologies is a strong plus
• Background supporting advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement is highly valued
• Knowledge of functional safety standards and automotive test requirements is a plus
• Contributions to industry test standards, technical publications, patents, or conference presentations strengthen your candidacy

Who You Are

• You can walk into a room with a customer's design team, diagnose a coverage gap in their hierarchical DFT strategy, and sketch a solution on the whiteboard that they trust enough to implement before tapeout
• You mentor engineers not by telling them what to do, but by asking the questions that help them see the tradeoff they missed between test time and pattern count
• You are comfortable presenting a methodology roadmap to a VP in two slides and then diving three levels deep with an engineer debugging an IJTAG network the same afternoon
• You push back when a proposed DFT architecture does not align with manufacturing realities, and you do it in a way that builds trust rather than friction
• You treat automation as a first-class deliverable, not an afterthought, because you know the methodology only scales if the Tcl actually works
• You stay current with industry trends, standards evolution, and emerging test challenges because you know that what worked on 7nm will not necessarily work on 3nm

The Team You'll Be Part Of

You will join the Digital Methodology Center of Excellence, a highly visible organization responsible for defining and advancing Synopsys' DFT methodologies, best practices, and customer deployment strategies. Working closely with R&D, product engineering, customer success, and strategic accounts, you will help shape the future of Design-for-Test and drive successful adoption of the industry's most advanced test solutions worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.