Senior Physical Design Engineer - Place and Route Implementation

Synopsys India Pvt Ltd; Bengaluru; Presencial; INR 4.200.000 - 6.400.000; Jornada completa

Descripción de la vacante

Synopsys India Pvt Ltd in Bengaluru is seeking a Staff Engineer, Physical Design to lead Place and Route implementation for advanced semiconductor designs, leveraging FC or Innovus and driving PPA improvements through flow optimization.

You will collaborate with global teams, debug complex issues, ensure robust signoff with ICV, PrimeTime, StarRC, and help scale automation of the implementation flow. We offer a collaborative environment and exposure to AI-assisted engineering tools.

Formación

• BS/B.Tech in EE/ECE or equivalent with 5+ years of experience, or MS/M.Tech with 3+ years.
• Strong hands-on experience in PnR design implementation and/or PnR flow methodologies.
• Understanding of PnR development flow and signoff tools.
• Experience with FC or Innovus and signoff tools such as ICV, RedHawk, PrimeTime, StarRC.
• Strong debugging, analytical, and collaborative skills across distributed teams.

Responsabilidades

• Drive Place and Route (PnR) implementation for complex semiconductor designs.
• Execute and optimize physical design flows across key stages of the PnR lifecycle.
• Work extensively with Fusion Compiler (FC) and/or Innovus for design implementation.
• Perform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC, or similar.
• Analyze implementation results and identify opportunities for PPA improvement.
• Contribute to continuous improvement of physical design flows, methodologies, and flow usage.
• Debug complex implementation and flow issues using strong analytical and problem-solving skills.
• Collaborate with engineering teams across different functions, geographies, and cultures.

Conocimientos

PnR design flow

Fusion Compiler

Innovus

Problem solving

Cross-cultural collaboration

Educación

BS/B.Tech in EE/ECE

MS/M.Tech in EE/ECE

Herramientas

Fusion Compiler

Innovus

ICV

RedHawk

PrimeTime

StarRC

Descripción del empleo

Staff Engineer, Physical Design General Information Job Title Staff Engineer, Physical Design Job ID 19236 Country India City Bengaluru Date Posted 12-Oct-2026 Job Category Engineering Job Subcategory ASIC Physical Design Hire Type Employee Remote Eligible No

Staff Engineer, Physical Design – PnR Implementation & Methodology

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies. You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus. You understand physical design signoff methodologies and have exposure to tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC , or equivalent solutions. Along with executing designs, you are interested in continuously improving implementation flows, methodologies, and Power, Performance, and Area (PPA). You bring strong debugging, analytical, and problem-solving capabilities and are comfortable collaborating with cross-cultural, geographically distributed, and matrixed engineering teams.

What You’ll Be Doing

• Drive Place and Route (PnR) implementation for complex semiconductor designs.
• Execute and optimize physical design flows across key stages of the PnR lifecycle.
• Work extensively with Fusion Compiler (FC) and/or Innovus for design implementation.
• Perform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC , or similar.
• Analyze implementation results and identify opportunities for PPA improvement.
• Contribute to continuous improvement of physical design flows, methodologies, and flow usage.
• Debug complex implementation and flow issues using strong analytical and problem-solving skills.
• Collaborate with engineering teams across different functions, geographies, and cultures.
• Explore productivity improvements through modern engineering and AI-assisted tools such as Cursor.

The Impact

Help deliver high-quality physical design implementation for advanced semiconductor designs. Improve Power, Performance, and Area (PPA) through design and flow optimization. Enhance the efficiency, robustness, and scalability of PnR implementation methodologies. Identify and resolve complex physical design and signoff issues. Contribute to continuous improvement and automation of implementation flows. Enable effective collaboration across global and cross-functional engineering teams.

What You’ll Need

• BS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 5+ years of relevant experience , OR MS/M.Tech in EE, ECE, or equivalent with 3+ years of relevant experience.
• Strong hands-on experience in PnR design implementation and/or PnR flow methodologies.
• Comprehensive understanding of the PnR development flow.
• Good hands-on experience with Fusion Compiler (FC) or Innovus.
• Good understanding of physical design signoff tools and methodologies.
• Experience or exposure to ICV, RedHawk, PrimeTime, StarRC , or similar tools.
• Experience contributing to PPA improvement and flow optimization activities.
• Strong debugging, analytical, and problem-solving skills.
• Excellent collaboration and influencing skills with the ability to work effectively in cross-cultural, multi-geography, and matrixed teams.
• Exposure to AI-assisted engineering tools such as Cursor is a plus.

Who You Are

You approach complex physical design challenges methodically and drive them through resolution. You enjoy debugging implementation, timing, physical verification, and flow-related issues. You look beyond basic design closure and continuously seek opportunities to improve PPA and implementation efficiency. You communicate technical issues clearly and collaborate effectively with geographically distributed teams. You are comfortable taking ownership while working as part of a broader engineering organization. You are curious about new methodologies, automation, and AI-assisted engineering approaches.

The Team You’ll Be Part Of

You will be part of a physical design engineering team focused on PnR implementation, design closure, signoff, flow methodology, and PPA optimization. You will collaborate with cross-functional and geographically distributed engineering teams to improve implementation quality, resolve complex design challenges, and continuously enhance physical design methodologies.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level Senior Level