Senior Lead Post-Silicon validation Engineer - SMMU

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Qualcomm India Private Limited is seeking a hands-on validation engineer to own IP- and subsystem-level verification of System MMU (SMMU) blocks within complex SoCs. You will work across ARM‑based architectures, MMU translation flows, and surrounding SoC infrastructure—from clocks and resets to NoC/fabrics and debug tools.

The role emphasizes coverage-driven testing, bring-up with JTAG and ETM/STM/SWO, and cross‑functional collaboration with architecture, RTL, firmware, and validation teams.

Qualifications

• Bachelor's or higher in Science/Engineering or related field with 3+ years ASIC design/verification/validation experience.
• Master's in Science/Engineering or related field with 2+ years ASIC experience.
• PhD in Science/Engineering or related field with 1+ year ASIC experience.

Responsibilities

• Own SMMU validation at block/IP and subsystem levels with coverage-driven test planning and closure.
• Develop reusable verification components for SMMU, including page table generators and translation fault injectors.
• Validate interactions between SMMU, ARM cores, NoC/Interconnect, and clock/reset domains.
• Exercise page table formats: stage-1/2 translations, ASIDs/VMIDs, context banks, MSI/IOMMU operations.
• Debug issues using JTAG and on-chip debug/trace infrastructure (ETM/STM/SWO) and bring-up scripts.
• Contribute to emulation/FPGA post-silicon validation: port tests and board bring-up sequences.

Skills

ARM architecture

SMMU/IOMMU fundamentals

Python scripting

JTAG debugging

Verdi/DVE traces

Education

BE/B.Tech/M.Tech in ECE/EE/CS

3–5 years ASIC design/verification experience

Tools

OpenOCD/Arm Development Studio

Verdi

Veloce/RUMI

Perforce

Jira

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

We’re looking for a hands‑on validation engineer to own IP‑and subsystem‑level verification & validation of System MMU (SMMU) blocks within complex SoCs. You will work across ARM‑based architectures, MMU/SMMU translation flows, and the surrounding SoC infrastructure—clocks, resets, NoC/fabrics, coherency, and debug (JTAG)—to ensure functional correctness, performance, and robustness from pre‑silicon through post‑silicon phases.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

What You’ll Do (Key Responsibilities)

• Own SMMU validation at block/IP and subsystem levels: coverage‑driven test planning, stimulus development, checking/score boarding, and closure.
• Develop test build reusable verification components for SMMU, including page table generators, translation fault injectors, and traffic generators.
• Validate system interactions: SMMU with ARM cores, MMU/TLB, NoC/Interconnect, coherency (ACE/CHI or equivalent), and clock/reset domains (including CDC and low‑power/clock‑gating scenarios).
• Exercise page table formats and features: stage‑1/stage‑2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, address translation faults, and SVA/ATS (if applicable).
• Debug complex issues using JTAG and on‑chip debug/trace infrastructure (ETM/STM/SWO), bring‑up scripts, and logic analyzers; drive root cause with design/architecture teams.
• Performance & stress validation: create stress scenarios (burst/atomic/ordering/ QoS), measure bandwidth/latency, and validate backpressure & throttling behavior through NoC.
• Contribute to emulation/FPGA and post‑silicon: port tests, build bare‑metal validation, develop board bring‑up sequences and lab automation.
• Own quality metrics: functional coverage, code coverage, assertions, defect density/escape rates; author clear test/coverage reports and sign‑off criteria.
• Collaborate cross‑functionally with architecture, RTL design, firmware/driver, physical design, and validation teams to refine specs and close issues quickly.
• Continuously improve methodology, tools, and checkers; mentor junior engineers in best practices.

Minimum Qualifications (Must‑Haves)

• B.E/B.Tech/M.Tech in ECE/EE/CS or equivalent with 3–5 years of relevant experience.
• Strong ARM architecture knowledge (A-profile preferred): memory model, privilege levels, exception model, caches, TLBs, MMU concepts, and virtual memory flows.
• Deep understanding of SMMU/IOMMU fundamentals: stream IDs, context banks, translation stages, page table formats, fault handling, and device DMA interactions.
• Familiar with NoC/interconnect protocols and coherency (e.g., AXI/ACE/CHI), ordering rules, QoS, and interop with SMMU.
• Solid grasp of clocks/resets and their impact on SMMU and NoC behavior; experience validating low‑power states and clock gating effects.
• JTAG basics to intermediate: scan chains, boundary scan, run‑control, breakpoints, basic scripting with OpenOCD/DS‑5/Arm Development Studio or similar.
• Proficient in debugging complex HW/SW issues, using waveforms (e.g., Verdi/DVE), traces, and logs to isolate root cause.
• Scripting in Python/Perl/TCL/Shell for test automation, log parsing, and lab workflows.
• Critical thinking & learning agility: ability to infer failure modes from first principles, design edge‑case tests, and quickly onboard new IP/flows.

Preferred Qualifications (Good‑to‑Have)

• Prior tapeouts with SMMU or IOMMU IP (Arm SMMU v2/v3 or equivalent vendor IP).
• Post‑silicon validation experience: lab bring‑up, firmware integration, board‑level debug.
• Experience with emulation/FPGA prototyping (Veloce, Palladium, Protium, HAPS).
• Familiarity with Linux IOMMU framework, device trees/ACPI, and driver‑level validation (DMA mappings, iommu_ops).
• Knowledge of PCIe (including ATS/PRI/PASID), CXL, or virtualization stacks (KVM/Hypervisors) and their interaction with SMMU.
• Exposure to safety/security: memory isolation, SMMU faults as security boundaries, RAS features, error injection and detection.
• Performance modeling/analysis; profiling tools; building synthetic traffic to characterize SMMU/NoC behavior.
• CI/CD for verification (Jenkins/GitLab CI), coverage dashboards, and regression triage at scale.

Tools & Environment

• Languages/Methodology: ARM assembly, C for bare‑metal tests, Python/TCL/Perl for scripting.
• Emu/FPGA: Veloce/RUMI
• Versioning/CI: Perforce, Jira.
• OS/Drivers: bare‑metal frameworks.

Key Performance Indicators (KPIs)

• Test plan completeness and functional/code coverage closure against SMMU spec and use‑cases.
• Defect discovery rate and escape rate (pre‑vs. post‑silicon).
• Time‑to‑root‑cause for complex issues; quality of triage documentation.
• Regression stability and automation coverage.
• Performance validation completeness vs. targets (latency, bandwidth, QoS).

Example Work Items You’ll Own

• Create tests for stage‑1 and stage‑2 translations, ASID/VMID rollover, TLB shootdowns, and context switch stress.
• Validate device DMA through SMMU under NoC congestion and clock gating scenarios; confirm ordering and coherency guarantees.
• Run JTAG‑based bring‑up sequences to verify SMMU registers, enable translations, and capture trace for fault analysis.
• Automate validation: configure IOMMU groups, map/unmap devices, inject faults, and parse kernel logs for health signals.

Education

• B.E/B.Tech or M.E/M.Tech in EE/ECE/CS (or equivalent).

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