Senior Engineer - Physical Design

SiFive India; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

SiFive India is seeking a Senior Physical Design Engineer to be a core technical contributor responsible for the physical design implementation of next‑generation IPs. You will drive RTL2GDS and push the architecture and design to peak physical potential.

We want a full‑stack PD engineer who thrives at the intersection of microarchitecture and layout, identifying timing bottlenecks, optimizing power, performance and area, and mentoring junior engineers while improving flows and automation.

Qualifications

• Experience: 4+ years of hands-on physical design on advanced process nodes (7nm and below preferred).
• IP Implementation Expertise: solid experience with the physical implementation of at least one major IP domain and the ability to adapt to new logic classes.
• Co-Design Mindset: understanding the interplay between physical implementation and microarchitecture.
• Tool Proficiency: industry-standard EDA tools, Synopsys Fusion Compiler, PrimeTime and Cadence Innovus/Tempus.
• Advanced Problem Solving: debug complex physical design challenges including timing violations and routing congestion.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

• End-to-End Implementation: Own and execute the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub-systems and IP blocks.
• Architectural & RTL Co-Optimization: Collaborate with RTL and Architecture teams to address bottlenecks.
• Cross-Product PPA Execution: Apply advanced PD techniques across design classes for power, performance and area.
• Technical Ownership: Own complex implementation challenges and mentor junior engineers.

Skills

Physical design

RTL collaboration

Co-design mindset

Problem solving

Mentoring

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

Cadence Innovus

Tempus

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive's phenomenal success and to see why we have won the GSA's prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

About the Role:

As a Senior Physical Design Engineer, you will be a core technical contributor responsible for the physical design implementation of our next‑generation IPs. In this role, you will implement RTL2GDS ensuring the architecture and design achieve their peak physical potential.

We are looking for a "full-stack" physical design engineer who is deeply curious about the logic they are building. You should be the type of engineer who thrives at the convergence of microarchitecture and physical layout, enjoying the challenge of analyzing how an architectural datapath affects timing closure and how to push the boundaries of Power, Performance, and Area (PPA).

Key Responsibilities:

• End-to-End Implementation: Own and execute the complete physical design flow (Synthesis, Floorplanning, P&R, Signoff) for major sub‑systems and diverse IP blocks, ensuring they meet or exceed aggressive targets for PPA.
• Architectural & RTL Co-Optimization: Partner with RTL and Architecture teams from early-stage design to signoff. Identify physical and structural bottlenecks early‑such as routing congestion in complex crossbars, dynamic power hot‑spots in execution units, and interconnect span limits‑and collaborate on microarchitectural or structural solutions to overcome them.
• Cross-Product PPA Execution: Apply advanced physical design techniques customized to the unique demands of different design classes. This includes implementing extreme leakage/dynamic power efficiency for edge IPs, rigorous reliability and redundancy structures for automotive standards, or maximizing bandwidth and throughput for high-speed fabrics.
• Technical Ownership: Take ownership of complex implementation challenges, contribute to the improvement of flows, methodology, and automation, and assist in mentoring junior engineers while promoting best practices.

Requirements - What you'll bring

• Experience: 4+ years of hands‑on physical design experience on advanced process nodes (7nm and below preferred).
• IP Implementation Expertise: Solid experience with the physical implementation of at least one major IP domain (such as CPUs, high-speed interconnects/fabrics, cache/memory hierarchies, or specialized accelerators) and a proven ability to adapt to new logic classes.
• Co-Design Mindset: Understanding of the interplay between physical implementation and microarchitecture, coupled with the curiosity to learn and adapt to different product architectures.
• Tool Proficiency: Strong proficiency with industry-standard EDA tools‑specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign-off suites.
• Advanced Problem Solving: Ability to debug complex physical design challenges, including structural timing violations, routing congestion etc. with minimal supervision.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Why join us?

In this role, you will play a pivotal part in driving aggressive PPA optimizations across significant design sections, operating at the critical intersection of physical layout, RTL design, and hardware architecture. You will have the autonomy to make a substantial impact across our entire product portfolio‑from highly efficient IoT cores and dense memory systems to demanding high-performance platforms. We offer a direct path for technical growth, allowing you to collaborate with world‑class engineers in a supportive, fast‑paced, and learning‑rich environment.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Any offer of empl