Senior Engineer II - CAD (Physical Verification)

Microchip Technology; India; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Microchip Technology is seeking a senior PV/physical verification engineer to reinforce the CAD group. You will develop regression tests and support backend PV activities across multiple PDKs for diverse process technologies, using Calibre, Pegasus and Hercules.

You will apply SVRF/TVF and contribute to debugging PV issues, rule development, and ensuring manufacturability and reliability of designs. Collaborative, globally distributed team environment offered.

Qualifications

• Bachelors with 7–8 years experience developing and supporting physical verification activities, or Masters with 5–6 years experience.
• In-depth knowledge of Calibre DesignRev scripting.
• Fluent with SVRF and TVF.
• Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer.
• Familiar with Tcl/Tk, Perl, Python and other programming languages, inside and outside EDA tools.
• Solid knowledge of layout rules, device identification concepts, and foundry rules.
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs.
• Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool.
• Strong knowledge of Cadence Virtuoso and/or CalibreDRV.
• Prefer Extraction, Reliability and Dynamic Noise related knowledge.
• Excellent verbal and written communication and interpersonal skills.

Responsibilities

• Develop physical verification regression test cases for multiple PDKs across process technologies.
• Support Layout and Design engineers with physical verification activities using industry tools (Calibre, Pegasus, Hercules).
• Apply advanced EDA methods to support ESD, ERC, V-W DRC, via-doubling and related checks.
• Collaborate with Technology Development and Device Engineering to develop DRC rules and manufacturability checks.
• Develop rule decks to support flow and verification.
• Verify and enhance foundry rule decks.
• Support remote sites worldwide with layout verification activities.
• Assist in debugging physical verification issues and improving device reliability.

Skills

SVRF

TVF

PV issue debugging

Strong communication

Education

Bachelor’s degree or higher

Tools

Calibre DesignRev scripting

Calibre Interactive (Tcl/Tk)

Perl

Python

Cadence Virtuoso

CalibreDRV

Pegasus

Hercules

RVE

Vue

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description:

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you.

The candidate will:

• Develop physical verification regression test cases to QA physical verification decks
• Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
• Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
• Develop rule decks as needed to support flow
• Verify and enhance foundry rule decks
• Support remote sites worldwide with layout verification activities
• Support debug of physical verification issues
• Work as a member of team to develop flows to improve quality and reliability of devices

The tasks this candidate will be assigned depends on their experience. There are several areas in which we are shorthanded. Potential task assignments would include:

• Building of regression test cases for several PDKs of various process technologies
• Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
• Calibre/Pegasus PERC - several PDKs still require PERC setup.

Requirements/Qualifications:

• Bachelors with 7 to 8 years experience developing and supporting physical verification activities, or Masters with 5 to 6 years experience developing and supporting physical verification activities
• In depth knowledge of Calibre DesignRev scripting
• Fluent with SVRF and TVF
• Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer
• Familiar with customizing Calibre Interactive Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools
• Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs
• Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool
• Strong knowledge of Cadence Virtuoso and/or CalibreDRV
• Prefer Extraction, Reliability and Dynamic Noise related knowledge
• Excellent verbal and written communication and interpersonal skills

Travel Time:

0% - 25%

To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.