Senior Design Verification Engineer - Microcontroller Units (MCU)

Renesas Electronics India Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Renesas Electronics India Pvt Ltd in Bengaluru is seeking a Senior Engineer in Design Verification to lead end-to-end verification of MCU-based SoCs, working across IPs and subsystems. You will define verification strategies, develop UVM environments, and drive coverage, constraints, and sign-off while collaborating with RTL, architecture, and emulation teams.

Experience in SystemVerilog, UVM, and MCU peripherals, plus AI-assisted verification, will help accelerate delivery in a fast-growing

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering.
• 2 - 4 years of experience in SoC Verification domains and knowledge of industry-standard EDA toolkits.
• Strong expertise in UVM-based testbench architecture and development.
• Proven experience in metric-driven verification including functional and code coverage closure.
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices.
• Experience with directed and constrained-random verification methodologies.
• Experience debugging complex design issues in simulation, emulation, and post-silicon environments.
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, and Shell scripting.
• Experience in verification of MCU-based SoCs and subsystems, including CPU cores, buses, and embedded peripherals.
• Strong understanding of MCU architectures such as ARM Cortex-M or RISC-V.
• Knowledge of firmware-driven verification techniques and embedded software interaction with MCU peripherals is desirable.
• Strong analytical, problem-solving, and communication skills.

Responsibilities

• Be a part of end-to-end verification execution for SOC owning complex digital IPs and subsystems from specification to sign-off.
• Define and drive IP-level verification strategies, including test plans, coverage models, and closure criteria.
• Develop scalable, reusable UVM-based verification environments for IP and subsystem verification.
• Lead functional, code, assertion, and cross-coverage closure, ensuring high-quality sign-off with clear metrics.
• Apply AI/ML-assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency.
• Drive constraint random and directed test methodologies for thorough protocol, corner-case, and stress verification.
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration.
• Review IP specifications and translate requirements into robust verification plans and checkers.
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors.
• Work with EDA vendors to evaluate and adopt next-generation verification tools.
• Mentor junior engineers and promote best-in-class verification practices.
• Support Gate-Level Simulation (GLS), low-power verification, and post-silicon debug when required.

Skills

UVM TB

SystemVerilog

Verilog

C/C++

Shell scripting

MCU peripherals

Education

Bachelor’s in Electronics Engineering

Tools

EDA toolkits

Job description

Senior Engineer, Design Verification (MCU) Company Description Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies. Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Job Description

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering.
• 2 - 4 years of experience in SoC Verification domains and working knowledge of industry‑standard EDA toolkits.
• Strong expertise in UVM‑based testbench architecture and development.
• Proven experience in metric-driven verification, including functional and code coverage closure.
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices.
• Experience with directed and constrained‑random verification methodologies.
• Experience debugging complex design issues in simulation, emulation, and post‑silicon environments.
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, and Shell scripting.
• Experience in verification of MCU‑based SoCs and subsystems, including CPU cores, AHB/APB/AXI bus protocols, interrupt controllers, GPIO, timers, UART, SPI, I2C, CAN, low‑power features, and embedded peripherals.
• Strong understanding of MCU architectures such as ARM Cortex‑M, RISC‑V, or equivalent embedded processor architectures.
• Knowledge of firmware‑driven verification techniques and embedded software interaction with MCU peripherals is desirable.
• Strong analytical, problem‑solving, and communication skills.

Preferred/Plus Qualifications

• Hands‑on experience using AI/ML‑based verification tools for: Coverage gap analysis
• Test stimulus optimization
• Regression triage and coverage acceleration
• Scripting expertise in Python, Perl, or TCL for automation and analytics.
• Exposure to formal verification and hybrid formal‑simulation flows.
• Familiarity with high‑speed or complex IPs, such as: H.264 Security, debug, or safety‑critical IPs
• Experience with MCU functional safety concepts (ISO 26262), low‑power verification, secure boot, and embedded system validation is a plus.
• Experience with firmware development/debugging in Embedded C or RTOS‑based environments is desirable.
• Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

Additional Information

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Experience Level

Senior Level

Equal Opportunity Statement

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement