Senior Design Verification Engineer

Tecquire Solutions; Dadri; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Tecquire Solutions is seeking a verification engineer to design and implement SOC verification using SystemVerilog/UVM. You will develop testbenches, write directed and constrained-random tests, and drive coverage closure with assertions and functional coverage.

Familiarity with AMBA protocols and power-aware verification is preferred. With 2–8 years of related experience, you will debug RTL/testbench issues and support silicon bring-up in a fast-moving India-based team.

Qualifications

• BTech/MTech with 2-8 years of experience in verification.
• Hands-on experience in SOC level test bench and test plan development.
• Knowledge of Amba Protocols.
• Experience in UVM/SystemVerilog-based verification.
• Power-aware verification and coverage-driven verification.

Responsibilities

• Build and maintain UVM/SystemVerilog-based testbenches.
• Functional Verification.
• Write directed and constrained-random test cases.
• Use assertions and functional coverage to validate design behavior.
• Debug simulation failures and root-cause issues in RTL or testbench.
• Power Aware Verification.
• Coverage and Assertion Closure.

Skills

SystemVerilog

UVM

Coverage development

Assertion development

Power-aware verification

Directed testing

Constrained-random testing

Education

BTech / MTech

Tools

Amba Protocols

Job description

Required Education: BTech/Mtech with Min. 2-8yrs of Exp.

3.Hands on experience in SOC level test bench and test plan development.

4.Knowledge of Amba Protocols

Key Words:

Advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development, Power-Aware verification

Required exp of 2 to 8 years

• Build and maintain UVM/SystemVerilog-based testbenches.
• Functional Verification
• Write directed and constrained-random test cases.
• Use assertions and functional coverage to validate design behavior.
• Debug simulation failures and root-cause issues in RTL or testbench.
• Power Aware Verification
• Coverage and Assertion Closure

Job Description:

Candidate will be responsible for verification plan definition, DV environment development in SV/UVM, SV/C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level, System scenario and use case verification, Power and performance analysis for your blocks in SOC, Gate level verification, Functional test vector development and Silicon bring up debug support.