Senior Design Verification Engineer

Texas Instruments Incorporated; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Texas Instruments Incorporated in Bengaluru is seeking a Design Verification Engineer to verify analog and mixed‑signal designs for hardware systems, from specs to post‑silicon verification and customer issue resolution.

You will define verification strategy, create a plan to meet full spec regression traceability, own DV environments, TBs and coverage using UVM, and collaborate across Architecture, RTL, PD, DFT, Systems, and firmware teams.

Job description

Change the world. Love your job.
Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/Full chip DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis.

This includes:

• Active involvement with architecture team during the spec definition phase
• Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics
• ip/Full chip verification covering functional and firmware scenarios in RTL and GLS.
• DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM
• Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities