Senior DAC Architect

Mulya Technologies; Bengaluru; Hybrid; INR 3,000,000 - 6,500,000; Full time

Job summary

Mulya Technologies in Bengaluru (Hybrid) seeks a Senior DAC Architect and Lead to drive high-performance DAC development from spec to production, interfacing with customers to capture requirements and translate them into silicon.

You will supervise transistor-level design, layout, and silicon evaluation in advanced CMOS processes, guiding teams across geographies and ensuring on-time product introductions to market.

Qualifications

• 10–20 years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes.
• Experience with high-speed, high-resolution ADC/DAC data converters and building blocks (bandgap, op-amps, comparators, DLL/PLL).
• Track record of taking designs to production.
• Ability to work with customers to define products addressing needs.
• Experience with bench evaluation and standard lab equipment.
• Strong transistor-level design intuition with noise and mismatch analysis.
• Experience with analog/digital behavioral modeling or synthesis of digital control blocks.
• Familiar with Cadence schematic capture, Virtuoso, Spectre and/or HSPICE.
• MATLAB understanding preferred.
• Familiar with EM/ESD design in submicron CMOS and layout parasitic extraction.
• Ability to work independently and adhere to schedules.
• Strong written and verbal communication for cross-geo teams.
• Proactive in seeking help and sharing knowledge.

Responsibilities

• Lead DAC development from initial specification to production release.
• Collaborate with customers to define product requirements.
• Oversee transistor-level design, layout supervision, and silicon evaluation.
• Guide cross-geo teams to ensure on-time market introduction.

Skills

Analog/Mixed-signal IC design

High-speed DAC/ADC design

Production release experience

Customer collaboration

Bench testing

Transistor-level design

Behavioral modeling

Cadence tools

MATLAB skills

EM/ESD design

Layout parasitic extraction

Self-management

Communication skills

Mentoring / knowledge sharing

Education

Masters/PhD in Electrical Engineering

Tools

Cadence Suite

Spectre

HSPICE

Job description

Hybrid

We are at the forefront of Wideband Signal Processing™ delivering high-performance, low-power analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other mixed-signal IP cores. These components are crucial for a wide array of modern applications, including artificial intelligence (AI) infrastructure, advanced wireless communications like:

• 5G networks and optical communications
• Automotive networking, LiDAR, and radar systems
• SatComm, Software Defined Radio (SDR) and other broadband communications

Senior DAC Architect and Lead

Engineering – IP Architecture /

Full-time /

DAC architect and development lead focusing on high-performance digital-to-analog converters. The successful candidate in this role will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

• 10-20years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes
• Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc.
• Must have a track record of successfully taking designs to production
• Ability to work with customers to define products that address needs
• Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
• Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks
• Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
• MATLAB understanding would be preferred but not mandatory
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process
• Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes
• Must be able to work independently, create and adhere to schedules
• Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations
• Should be able to seek help proactively as well as share and pass on knowledge