Senior AMS Verification Architects

Eximietas Design; Visakhapatnam; On-site; INR 15,00,000 - 25,00,000; Full time

Job summary

A leading design firm is seeking experienced Senior AMS Verification Leads & Architects in Visakhapatnam. The role involves leading AMS verification activities, ensuring compliance with design specifications, and collaborating with design teams. Candidates should have over 15 years of experience and be fluent in System Verilog, with strong knowledge of analog IPs. Interested candidates should share their resumes at the provided email address.

Qualifications

• 15+ years of AMS design verification experience.
• Experience with developing verification methodologies and automation.
• Good understanding of CMOS and VLSI technologies.

Responsibilities

• Lead AMS verification and ensure compliance with specifications.
• Architect and automate test benches for pre-silicon designs.
• Collaborate with designers to meet system requirements.

Skills

Fluent in System Verilog

Proficient with scripting languages (Python, Tcl, Perl)

Understanding of analog IPs

Education

Bachelor’s degree in Electrical Engineering or relevant field

Tools

Cadence Spectre

AMS simulator

Job description

🚀 Hiring: Senior AMS Verification Leads & Architects

📍 Location: Bengaluru / Visakhapatnam

🏢 Company: Eximietas Design

💼 Eximietas Hiring : Senior AMS Verification Architects - 15+ Years

Job Description:

Responsibilities:

• Lead AMS, including reviewing design specifications and defining and executing a verification plan to ensure compliance with specifications.
• Architect, implement, and automate analog, digital, and AMS test benches to verify pre‑silicon designs.
• Build System Verilog real number analog behavioral models, monitors, and checkers for DMS/AMS design.
• Work closely with analog, digital, and system designers to verify the implementation meets system requirements.
• Collaborate with digital design verification engineers to architect and implement tests to verify analog/digital interfaces.
• Lead the development of AMS simulation and verification methodologies.

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, relevant technical field, or equivalent practical experience.
• 15+ years of AMS design verification experience.
• Fluent in System Verilog and real number modeling.
• Experience with Cadence Spectre and AMS simulator.
• Proven understanding of analog IPs, including Bandgap, oscillator, ADC/DAC, LDO, PLL, and Serdes.
• Proficient with a scripting language, such as Python, Tcl, or Perl is mandatory.

Preferred Qualifications:

• Experience in developing verification methodology, flows, and automation.
• Experience with AMS chip bring‑up and debug.
• Analog/Mixed Signal Circuit verification experience with tape‑out experience in several of the following: LDO, DC‑DC converters, Bandgap, A/D and D/A conversion, Tempsensor, PLLs, etc.
• Good understanding of CMOS and VLSI technologies (device physics, layout effects, sub‑micron effects, and device reliability).

Location: Visakhapatnam, Andhra Pradesh, India

Interested Engineers, please share your updated resume: [e-mail]

If this opportunity excites you—or if you know someone who may be a great fit—please share your updated resume at: 📧 [e-mail]

Referrals are highly appreciated!

Looking forward to connecting with talented engineers who are passionate about advancing analog layout design.