RTL Engineer

Eridu; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Eridu is seeking experienced RTL designers to define and implement Networking ASICs. As part of the Design Group, you will define, specify, architect, execute, and productize cutting-edge networking chips.

Responsibilities include packet buffering, queuing, scheduling, on-chip memory considerations, verification, and performance optimization. You will collaborate with cross‑functional teams to ensure high reliability and scalable interconnects including UCIe.

Qualifications

• 8+ years of RTL engineering experience.
• Hands-on SystemVerilog and Verilog experience.
• Strong understanding of ASIC design methodologies including simulation, verification, synthesis, and timing.

Responsibilities

• Packet buffering, queuing, and scheduling for high-speed networking ASICs with latency optimization and QoS support.
• Implement designs on ASIC platforms and validate with verification teams.
• Analyze and optimize pipelining architectures to improve performance.
• Provide protocol support for Ethernet/IP and high-speed interconnects like UCIe.
• Troubleshoot and debug complex networking issues with cross-functional teams.

Skills

SystemVerilog

Verilog

Scheduling QoS

ASIC design

Ethernet

IP protocols

RTL design

Education

Bachelor of Engineering

Job description

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Position Overview

We are seeking experienced RTL designers to help define and implement our industry‑leading Networking ASIC’s. If you're a highly motivated self‑starter eager to solve real‑world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting‑edge Networking chips.

Responsibilities

Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on‑chip memory subsystem and scheduling / arbitration design.

Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.

Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.

Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.

Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross‑functional teams, including system architects, hardware engineers, and firmware developers.

Minimum Qualifications

• 8+ years of experience in RTL engineering related roles
• Hands‑on knowledge of SystemVerilog and Verilog
• Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments
• Proven expertise in designing and optimizing scheduling and QoS mechanisms
• Experience with Ethernet and IP protocols
• Bachelors of Engineering

Preferred Qualifications

• 8+ years of experience
• Strong analytical and problem‑solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
• Masters of Engineering

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.