Principal System on Chip (SoC) Design Lead Engineer

Globalfoundries Engineering Private Limited; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

GlobalFoundries is seeking a Senior Principal SoC Design Lead to own architecture, microarchitecture, and RTL delivery for complex SoCs in Smart Analog & Sensor products. You will lead IP integration, subsystem development, and cross‑functional teams from concept to silicon, shaping next‑gen platform architectures for multiple customer products.

Ideal candidates bring 15+ years of experience, deep RTL expertise, and a track record of driving architecture decisions, performance/power/area

Qualifications

• Minimum BS degree and 15+ years of relevant experience.
• Experience architecting and delivering complex SoCs.
• Expertise in RTL with Verilog/SystemVerilog.
• Experience with memory hierarchies, NoCs, and system integration.
• Ability to analyze performance, power, and area tradeoffs.

Responsibilities

• Define SoC architecture and subsystems aligned with product requirements.
• Lead RTL implementation and integration across teams.
• Collaborate with verification, DFT, and physical design to meet objectives.
• Drive platform roadmaps and reusable architectures.
• Lead post-silicon debug and root-cause analysis.

Skills

SoC architecture

RTL development (Verilog/SystemVerilog

Memory hierarchies & NoCs

System integration

Performance-power-area tradeoffs

Education

Bachelor's degree

Job description

Principal Engineer SoC Design Lead Principal SoC Design Lead

About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com .

Build the Next Generation of Advanced Sensor Platforms at GF

At MIPS by GF Custom Silicon Business, we are developing highly integrated Advanced Sensor Platform solutions that combine compute, signal processing, connectivity, security, safety, and software into differentiated semiconductor products for our customers. Our teams span architecture, modeling, RTL development, verification, physical implementation, software, test, and product engineering. We bring together experts from multiple disciplines to solve challenging power, performance, area, safety, security, and cost optimization problems while delivering highly scalable and reusable platform solutions.

Introduction:

The Principal SoC Design Lead is responsible for the architecture, microarchitecture, integration, and delivery of complex SoCs for Smart Analog & Sensor products. This individual serves as the technical leader for one or more SoC programs, driving IP integration, subsystem development, RTL quality, and cross-functional execution from concept through silicon. The role requires strong expertise in processor-based SoCs, subsystem architecture, RTL development, and SoC integration, combined with the ability to lead technical teams across multiple disciplines. We are seeking seasoned SoC Design / RTL Lead who combines strong architectural vision with deep hands‑on RTL experience. The successful candidate will play a pivotal role in defining and delivering next‑generation platform architectures that enable multiple customer products and future derivatives. Join us and put your skills, insight, and passion to redefine what’s possible.

Key Responsibilities

• Definition and ownership of SoC architecture spanning processing subsystems, memory hierarchy, NoC/interconnect, clocking, reset, interrupt and event infrastructure, interfaces, and peripherals.
• Development of microarchitectural specifications from architectural exploration through implementation-ready design specifications
• Ownership of system-level performance, power and area tradeoffs
• Definition and integration of subsystem interfaces across compute, datapath, safety, security, software and peripheral domains
• Technical leadership of RTL implementation teams and convergence of architecture into production-quality RTL
• Collaboration with verification, DFT and physical design teams to achieve project objectives
• Contribute to platform roadmaps and reusable SoC architectures
• Review microarchitecture and RTL implementation of critical blocks.
• Drive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.
• Evaluate, select, and integrate internal and third-party IP and establish IP reuse methodologies
• Drive closure of functionality, timing, power, and integration objectives.
• Support post-silicon debug and root-cause analysis.
• Mentor RTL and integration engineers.
• Lead technical reviews and design signoffs.
• Influence engineering methodology and best practices across the organization.

Key responsibilities

• SoC Architecture & Planning Define SoC and subsystem architectures aligned with product requirements.
• Drive hardware partitioning across processors, accelerators, memories, and peripherals.
• Lead architecture tradeoff analyses covering performance, power, area, security, and scalability.
• Contribute to platform roadmaps and reusable SoC architectures.
• RTL & Integration Leadership Lead development of complex RTL subsystems and top-level integration.
• Define SoC integration methodologies and quality standards.
• Review microarchitecture and RTL implementation of critical blocks.
• Drive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.
• IP Strategy Evaluate, select, and integrate internal and third-party IP.
• Establish IP reuse methodologies across multiple product generations.
• Ensure robust SoC assembly and subsystem interoperability.
• Silicon Execution Lead execution from specification through tapeout and silicon bring-up.
• Drive closure of functionality, timing, power, and integration objectives.
• Support post-silicon debug and root-cause analysis.
• Technical Leadership Mentor RTL and integration engineers.
• Lead technical reviews and design signoffs.
• Influence engineering methodology and best practices across the organization.

Minimum Qualifications

• Minimum BS and 15+ years of relevant industry experience
• Experience architecting and delivering complex SoCs
• Experience with memory hierarchies, NoCs, bus architectures and system integration
• Expertise in RTL development using Verilog or SystemVerilog
• Experience with architecture-performance-power-area tradeoff analysis

Preferred Qualifications

• Experience with automotive or safety-critical systems
• Experience with multicore systems
• Experience with security and functional safety architectures
• Experience leading cross-functional engineering teams
• Experience with advanced implementation and signoff flows

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce.

We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Experience Level Senior Level