Principal SoC Signoff Engineer

GlobalFoundries inc.; India; Sur place; INR 450 000 - 750 000; Plein temps

Avantages offerts par ce poste

Health insurance

Résumé du poste

GlobalFoundries in India seeks a Principal Engineer, SoC Signoff to own timing-constraint development for complex SoCs and IPs, spanning digital, analog, and mixed-signal interfaces. You will define signoff margins from specification to production and mentor a high-performing team.

Lead multi-voltage and DVFS signoff, drive shift-left STA methodologies with EDA partners, and apply AI/ML-enabled STA techniques. Strong UPF/SDC expertise and leadership and communication skills are essential.

Qualifications

• 12+ years of industry experience with STA and SoC timing
• 2+ years subsystem RTL design
• 6+ years STA constraint development
• 4+ years STA signoff
• Expert constraints for MV/DVFS designs with UPF & SDC
• Experience with leading EDA tools (Synopsys, Cadence, Siemens)

Responsabilités

• Lead timing-constraint development for complex SoCs and IPs
• Define signoff margins for ASIC implementation and STA
• Establish MV/DVFS signoff processes and shift-left methodologies
• Mentor a high-performing engineering team
• Develop AI/ML-enabled STA methodologies with EDA partners

Connaissances

Timing constraints

STA signoff

Leadership

Mentoring

Problem solving

Communication

Formation

Bachelors/Masters EE/CE

Outils

Synopsys

Cadence

Siemens EDA

UPF

SDC

Description du poste

**Title****:** **Principal Engineer, SOC signoff****About GlobalFoundries**GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.**Introduction:**The Principal Engineer, SoC Signoff has a deep understanding about how timing constraints are to be written across functional and test modes. They not only leads but mentors engineers towards designing and delivering full chip, complex Ips, and critical interface multi-mode timing constraints. This role drives the creation of constraints for custom integrated circuits (ICs) from specifications, co-ordinate across stake holding teams not only to create constraints and validate them, but also define margin methodologies and develop process for every SoC design we develop at MIPS**Your Job*** Lead and own all phases of timing-constraint development for complex SoCs and digital, AMS, and SerDes IPs.* Define signoff margins for ASIC implementation and static timing analysis (STA), from specification through production.* Establish processes for multi-voltage and dynamic voltage and frequency scaling (MV/DVFS) STA signoff, and develop shift-left methodologies for STA.* Provide technical mentorship to a high-performing engineering team, including recent graduates.* Champion the development, deployment, and maintenance of AI/ML-enabled STA methodologies in collaboration with leading EDA partners * **Other Responsibilities*** Perform all duties safely and responsibly, and support all Environmental, Health, Safety, and Security requirements and programs. **Required Qualifications** * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.* 12+ years of industry experience, including at least 2 years in subsystem RTL design, 6 years in STA constraint development, and 4 years in STA signoff.* Deep, hands-on expertise in developing functional- and test-mode constraints for full-chip and sub-chip digital, analog, mixed-signal, and source-synchronous designs and interfaces.* Expertise in constraint development for MV/DVFS designs, with advanced proficiency in UPF and expert-level proficiency in SDC.Expertise in STA signoff margining and a demonstrated ability to establish signoff processes from the ground up.* Deep, hands-on experience executing STA signoff, including mode reduction and methodology infrastructure development.Proven experience conducting timing-signoff reviews for production SoCs.* Strong proficiency with leading EDA tools from Synopsys, Cadence, or Siemens EDA.Excellent leadership, mentoring, and communication skills* Strong analytical and problem-solving skills. **Preferred Qualifications** * Proven track record of delivering custom silicon across a range of application domains.* Inspirational leadership style, with a passion for mentoring and scaling high-performing teams.Customer-focused, proactive approach to problem-solving* Commitment to continuous learning and the adoption of industry best practices.* Expertise with the Synopsys EDA tool suite.Exposure to agentic AI technologies and workflows. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.To ensure that we maintain a safe and healthy workplace for our GlobalFoundries employees, please note that offered candidates who have applied for jobs in India will have to be fully vaccinated prior to their targeted start date.Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia