Principal Engineer SoC Design Lead

GlobalFoundries inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

GlobalFoundries seeks a Principal SoC Design Lead to own architecture, microarchitecture, integration and delivery of complex SoCs for Smart Analog & Sensor products. Lead IP integration and RTL teams from concept to silicon.

The role requires deep hands-on RTL experience with Verilog/SystemVerilog, expertise in NoC, memory hierarchy, timing, power, and area tradeoffs, and the ability to steer cross-functional teams across architecture, DV and physical design.

Qualifications

• Minimum BS and 15+ years of relevant industry experience.
• Experience architecting and delivering complex SoCs.
• Expertise in memory hierarchies, NoCs, bus architectures and system integration.
• Experience with architecture-performance-power-area tradeoff analysis.

Responsibilities

• Definition and ownership of SoC architecture spanning processing subsystems, memory hierarchy, NoC/interconnect, clocking, reset, interrupt and event infrastructure, interfaces, and peripherals.
• Lead RTL implementation teams and convergence of architecture into production-quality RTL.
• Review microarchitecture and RTL implementation of critical blocks.
• Drive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.
• Mentor RTL and integration engineers and lead technical reviews and design signoffs.

Skills

Verilog

SystemVerilog

RTL development

NoC

architecture-performance-power-area

multi-core SoCs

IP integration

Education

Bachelor's degree

Tools

Verilog

SystemVerilog

Job description

Principal SoC Design LeadAbout GlobalFoundriesGlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com .Build the Next Generation of Advanced Sensor Platforms at GFAt MIPS by GF Custom Silicon Business, we are developing highly integrated Advanced Sensor Platform solutions that combine compute, signal processing, connectivity, security, safety, and software into differentiated semiconductor products for our customers.Our teams span architecture, modeling, RTL development, verification, physical implementation, software, test, and product engineering. We bring together experts from multiple disciplines to solve challenging power, performance, area, safety, security, and cost optimization problems while delivering highly scalable and reusable platform solutions.Introduction:The Principal SoC Design Lead is responsible for the architecture, microarchitecture, integration, and delivery of complex SoCs for Smart Analog & Sensor products. This individual serves as the technical leader for one or more SoC programs, driving IP integration, subsystem development, RTL quality, and cross-functional execution from concept through silicon.The role requires strong expertise in processor-based SoCs, subsystem architecture, RTL development, and SoC integration, combined with the ability to lead technical teams across multiple disciplines.We are seeking seasoned SoC Design / RTL Lead who combines strong architectural vision with deep hands-on RTL experience. The successful candidate will play a pivotal role in defining and delivering next-generation platform architectures that enable multiple customer products and future derivatives.Join us and put your skills, insight, and passion to redefine what’s possible.Key ResponsibilitiesAs a SoC Design / RTL Lead, you will own or participate in the following:Definition and ownership of SoC architecture spanning processing subsystems, memory hierarchy, NoC/interconnect, clocking, reset, interrupt and event infrastructure, interfaces, and peripherals.Development of microarchitectural specifications from architectural exploration through implementation-ready design specificationsOwnership of system-level performance, power and area tradeoffsDefinition and integration of subsystem interfaces across compute, datapath, safety, security, software and peripheral domainsTechnical leadership of RTL implementation teams and convergence of architecture into production-quality RTLCollaboration with verification, DFT and physical design teams to achieve project objectivesContribute to platform roadmaps and reusable SoC architecturesReview microarchitecture and RTL implementation of critical blocks.Drive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.Evaluate, select, and integrate internal and third-party IP and establish IP reuse methodologiesDrive closure of functionality, timing, power, and integration objectives.Support post-silicon debug and root-cause analysis.Mentor RTL and integration engineers.Lead technical reviews and design signoffs.Influence engineering methodology and best practices across the organization.Key responsibilitiesSoC Architecture & PlanningDefine SoC and subsystem architectures aligned with product requirements.Drive hardware partitioning across processors, accelerators, memories, and peripherals.Lead architecture tradeoff analyses covering performance, power, area, safety, and scalability.Contribute to platform roadmaps and reusable SoC architectures.RTL & Integration LeadershipLead development of complex RTL subsystems and top-level integration.Define SoC integration methodologies and quality standards.Review microarchitecture and RTL implementation of critical blocks.Drive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.IP StrategyEvaluate, select, and integrate internal and third-party IP.Establish IP reuse methodologies across multiple product generations.Ensure robust SoC assembly and subsystem interoperability.Silicon ExecutionLead execution from specification through tapeout and silicon bring-up.Drive closure of functionality, timing, power, and integration objectives.Support post-silicon debug and root-cause analysis.Technical LeadershipMentor RTL and integration engineers.Lead technical reviews and design signoffs.Influence engineering methodology and best practices across the organization. Minimum QualificationsMinimum BS and 15+ years of relevant industry experienceExperience architecting and delivering complex SoCsExperience with memory hierarchies, NoCs, bus architectures and system integrationExpertise in RTL development using Verilog or SystemVerilogExperience with architecture-performance-power-area tradeoff analysisPreferred QualificationsExperience with automotive or safety-critical systemsExperience with multicore systemsExperience with security and functional safety architecturesExperience leading cross-functional engineering teamsExperience with advanced implementation and signoff flowsGlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia