Principal Engineer , DFT

Aitomic Jobs; Hyderabad; On-site; INR 6,000,000 - 12,000,000; Full time

Job summary

Renesas Electronics is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs. The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring-up and production test deployment.

Responsibilities include defining SoC-level DFT architecture and test strategy (Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, test compression), owning the complete DFT flow, silicon bring‑up,

Qualifications

• 15+ years of hands-on DFT experience with successful delivery of multiple SoCs.
• Strong knowledge of DFT architecture, test planning and sign-off.
• Experience with industrial EDA tools and automation

Responsibilities

• Define and drive SoC-level DFT architecture and test strategy including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.
• Own the complete DFT flow from architecture to RTL design, verification, scan insertion, ATPG, coverage closure and signoff.
• Drive silicon bring-up, debug and diagnosis, yield improvement and production test enablement.
• Develop scalable DFT methodologies, automation frameworks and best practices.
• Collaborate with Design, Verification, Physical Design and Test Engineering teams.

Skills

DFT engineering

ATPG & MBIST

LBIST & JTAG/IJTAG

RTL design & DFT integration

Automation frameworks

Leadership & mentoring

Tessent tooling

Scripting: Python/TCL/Perl/Shell

Education

B.E./B.Tech., M.E./M.Tech., or Ph.D. in Electronics or related field

Tools

Tessent

Genus/Fusion Compiler

VCS/Xcelium

Conformal/Formality

Job description

Short Summary

Principal Engineer , DFT with Renesas Electronics. Renesas is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs. The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring-up and production test deployment. Key Responsibilities Define and drive SoC-level DFT architecture and test strategy…

Key Details

• Position / opportunity: Principal Engineer , DFT
• Organization: Renesas Electronics
• Country / coverage: India
• Location: Hyderabad, , India
• Work arrangement: On-site
• Opportunity type: Jobs
• Sector: Health
• Compensation: Not specified
• Duration: Not specified
• Start date: 2026-08-18
• Application deadline: Not specified

Description

Renesas is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs. The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring-up and production test deployment. Key Responsibilities Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression. Own the complete DFT flow from test architecture, RTL design & integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff. Drive silicon bring‑up, silicon debug, diagnosis, yield improvement, and production test enablement. Develop and deploy scalable DFT methodologies, automation frameworks, and best practices. Collaborate with Design, Verification, Physical Design, and Test Engineering teams. Provide technical leadership and mentor engineers across projects. B.E./B.Tech., M.E./M.Tech., or Ph.D. in Electronics or related field. 15+ years of hands‑on DFT experience with successful delivery of multiple SoCs. Proven expertise in: DFT Architecture & Test Planning DFT RTL Design & Integration Scan Insertion & ATPG MBIST, LBIST, JTAG/IJTAG GLS & Signoff Silicon Bring‑up, Debug & Diagnosis Strong hands‑on experience with Tessent, Genus/Fusion Compiler, VCS/Xcelium, and Conformal/Formality. Strong automation and scripting skills using Python, TCL, Perl, or Shell. Leadership & Soft Skills Strong technical leadership with the ability to influence cross‑functional and global teams. Demonstrated ownership, accountability, and execution excellence. Excellent analytical, problem‑solving, and debugging skills. Proven mentoring and coaching capabilities to develop engineering talent. Self‑motivated, collaborative, and results‑oriented with a continuous improvement mindset. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .

Responsibilities

• Renesas is seeking a highly experienced Principal DFT Engineer to drive end-to-end DFT execution for advanced SoCs/MCUs.
• The candidate should possess deep expertise across the complete DFT lifecycle, from test architecture definition through silicon bring‑up and production test deployment.
• Key Responsibilities Define and drive SoC-level DFT architecture and test strategy, including Scan, ATPG, MBIST, LBIST, JTAG/IJTAG, SSN, and test compression.
• Own the complete DFT flow from test architecture, RTL design & integration, DFT verification, scan insertion, ATPG, coverage closure, and signoff.
• Drive silicon bring‑up, silicon debug, diagnosis, yield improvement, and production test enablement.
• Develop and deploy scalable DFT methodologies, automation frameworks, and best practices.

Requirements / Eligibility

• automation and scripting skills using Python, TCL, Perl, or Shell.
• Leadership & Soft Skills Strong technical leadership with the ability to influence cross‑functional and global teams.
• Demonstrated ownership, accountability, and execution excellence.
• Excellent analytical, problem‑solving, and debugging skills.