Principal Engineer, Design for Test (DFT)

Ayar Labs, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Ayar Labs, Inc. in Bengaluru, India is seeking a Principal DFT Engineer to lead architecture and implementation for complex electro-optical SoCs and chiplet systems.

You will drive DFT across scan, ATPG, MBIST/LBIST, JTAG, and fault coverage, working with RTL, Physical Design, and Validation teams to ensure high yield and production readiness. The role requires hands-on leadership in a fast-paced startup environment, guiding DFT execution from architecture through production ramp and

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/SoC DFT implementation and silicon bring-up.
• Strong expertise in: Scan architecture and scan compression, ATPG and fault coverage analysis, MBIST/LBIST methodologies, JTAG and boundary scan, At-speed testing and silicon debug and DFT signoff and manufacturing test flows.
• Strong knowledge of RTL-to-GDSII ASIC development flows.
• Experience with industry-standard DFT and ATPG tools.
• Strong understanding of timing constraints, clocking architectures, and multi-clock domain designs.
• Experience debugging silicon and supporting high-volume manufacturing.
• Strong scripting and automation skills using Python, Tcl, or similar languages.
• Excellent debugging, problem-solving, and cross-functional collaboration skills.

Responsibilities

• Define and drive SoC-level DFT architecture and implementation strategy for advanced ASIC and electro-optical SoCs.
• Lead scan insertion, ATPG generation, MBIST/LBIST integration, JTAG/boundary scan, and compression methodologies.
• Develop and validate DFT constraints, timing requirements, and test modes in collaboration with RTL and Physical Design teams.
• Drive fault coverage closure, pattern validation, and silicon test debug activities.
• Collaborate with ASIC, AMS, Packaging, Firmware, Validation, and Product Engineering teams to ensure successful silicon bring-up and production readiness.
• Develop automated methodologies, flows, and infrastructure to improve DFT quality and execution efficiency.
• Drive root-cause analysis for silicon test failures and manufacturing issues.
• Work closely with EDA vendors and external partners on DFT tool flows and methodologies.
• Mentor engineers and provide technical leadership across DFT and related domains.

Skills

Scan architecture

ATPG

MBIST/LBIST

JTAG/boundary scan

compression methodologies

DFT constraints

timing requirements

RTL-to-GDSII

DFT tools

Python scripting

Tcl scripting

debug silicon

cross-functional collaboration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

ATPG Tools

MBIST Tools

JTAG Tools

RTL-to-GDSII tools

Python

Tcl

Job description

Location: Bengaluru, India (On-site, flexible hours)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders and manufactured in partnership with the worlds leading semiconductor ecosystem, Ayar Labs' co-packaged optics solutions are enabling next-generation AI scale-up architectures.

The Principal DFT Engineer will lead Design-for-Test architecture, implementation, and silicon bring-up for complex electro-optical SoCs and chiplet-based systems. This role requires strong technical leadership across scan architecture, ATPG, MBIST/LBIST, silicon debug, and production test methodologies.

You will work closely with ASIC Design, AMS, Photonics, Physical Design, Validation, Firmware, and Product Engineering teams to deliver high-quality silicon with strong manufacturability, test coverage, and production readiness.

The ideal candidate is a hands-on technical leader who thrives in a fast-paced startup environment and can drive DFT execution from architecture definition through production ramp.

Key Responsibilities

• Define and drive SoC-level DFT architecture and implementation strategy for advanced ASIC and electro-optical SoCs
• Lead scan insertion, ATPG generation, MBIST/LBIST integration, JTAG/boundary scan, and compression methodologies
• Develop and validate DFT constraints, timing requirements, and test modes in collaboration with RTL and Physical Design teams
• Drive fault coverage closure, pattern validation, and silicon test debug activities
• Collaborate with ASIC, AMS, Packaging, Firmware, Validation, and Product Engineering teams to ensure successful silicon bring-up and production readiness
• Support post-silicon validation, characterization, yield analysis, and manufacturing ramp activitiesDevelop automated methodologies, flows, and infrastructure to improve DFT quality and execution efficiency
• Drive root-cause analysis for silicon test failures and manufacturing issues
• Work closely with EDA vendors and external partners on DFT tool flows and methodologies
• Mentor engineers and provide technical leadership across DFT and related domains

Required Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in ASIC/SoC DFT implementation and silicon bring-up
• Strong expertise in: Scan architecture and scan compression, ATPG and fault coverage analysis, MBIST/LBIST methodologies, JTAG and boundary scan, At-speed testing and silicon debug and DFT signoff and manufacturing test flows
• Strong knowledge of RTL-to-GDSII ASIC development flows
• Experience with industry-standard DFT and ATPG tools
• Strong understanding of timing constraints, clocking architectures, and multi-clock domain designs
• Experience debugging silicon and supporting high-volume manufacturing
• Strong scripting and automation skills using Python, Tcl, or similar languages
• Excellent debugging, problem-solving, and cross-functional collaboration skills

Preferred Qualifications

• Experience with advanced-node SoCs and chiplet-based architectures
• Experience with high-speed SerDes, UCIe, PCIe, CXL, Ethernet, or optical interconnect technologies
• Experience with mixed-signal integration and electro-optical systems
• Experience with silicon bring-up, yield improvement, and production ramp
• Familiarity with advanced packaging technologies and multi-die integration
• Experience working in startup or fast-paced product development environments
• Experience mentoring and leading geographically distributed engineering teams

What We Value

• Strong ownership and accountability
• Execution-focused mindset with high attention to quality and predictability
• Ability to drive complex technical problems to closure
• Collaborative leadership and mentoring capability
• Passion for building scalable methodologies and delivering production-quality silicon