Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

Synopsys Inc; Hyderabad; On-site; INR 2,800,000 - 4,200,000; Full time

Job summary

Synopsys India Pvt. Ltd. in Hyderabad seeks a Principal Digital Verification Engineer to design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA. You will draft test plans, develop reusable verification IP and testbenches, and close coverage gaps with design teams before tapeout.

You will mentor junior engineers, push for coverage closure, and validate designs using VCS, ModelSim or Xcelium in multi-protocol environments.

Qualifications

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8 to 10+ years of hands-on ASIC or SoC verification experience.
• Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs.
• Strong proficiency in SystemVerilog and UVM, including building testbenches, writing assertions, and developing verification IP.
• Experience with HBM2/HBM3, DDR4/DDR5, LPDDR4/LPDDR5 is a strong plus.

Responsibilities

• Design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM
• Write detailed test plans that cover functional scenarios, corner cases, and protocol compliance for memory controller and interface IP designs
• Develop reusable verification IP and testbenches that can be adapted across multiple projects and IP variants
• Work directly with design and architecture teams to identify bugs, clarify specifications, and close coverage gaps before tapeout
• Run functional coverage analysis, track metrics, and drive coverage closure across complex multi-protocol environments
• Mentor junior verification engineers on UVM best practices, debugging techniques, and verification strategy
• Use simulation tools like VCS or ModelSim to execute regression suites, debug failures, and validate design changes

Skills

SystemVerilog

UVM

Testbenches

Functional coverage

Mentoring

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

VCS

ModelSim

Xcelium

Job description

Job Title

Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the better part of a decade verifying complex ASIC designs, and you know that the hardest bugs are the ones that hide in corner cases three layers deep in a protocol handshake. You have worked on memory interfaces long enough to know that HBM, DDR, and LPDDR are not just acronyms, they are ecosystems with timing constraints, power states, and failure modes that can sink a tapeout if you miss them.

You do not wait for a design to be "ready" before you start thinking about verification. You are already mapping out testbenches, coverage models, and corner cases while the RTL is still being written. When something does not make sense in a spec, you ask. When a test fails in a way that should not be possible, you dig until you find the root cause, not just a workaround.

You have built verification environments from scratch and you have also inherited messy ones and made them better. You know how to balance thoroughness with schedule pressure, and you can explain a coverage gap to an architect without making it feel like blame. At this point in your career, you are not just verifying designs, you are shaping how verification gets done, mentoring engineers, and setting the standard for what good looks like.

What You'll Be Doing

• Design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM
• Write detailed test plans that cover functional scenarios, corner cases, and protocol compliance for memory controller and interface IP designs
• Develop reusable verification IP and testbenches that can be adapted across multiple projects and IP variants
• Work directly with design and architecture teams to identify bugs, clarify specifications, and close coverage gaps before tapeout
• Run functional coverage analysis, track metrics, and drive coverage closure across complex multi-protocol environments
• Mentor junior verification engineers on UVM best practices, debugging techniques, and verification strategy
• Use simulation tools like VCS or ModelSim to execute regression suites, debug failures, and validate design changes

The Impact You Will Have

• Deliver Interface IP that powers memory subsystems in AI accelerators, mobile SoCs, and high-performance computing platforms used across the industry
• Reduce post-silicon bugs and customer escalations by catching issues early through rigorous verification and coverage-driven testing
• Shape the verification methodology and standards that the team will use for the next generation of memory IP products
• Accelerate project schedules by building reusable verification components that cut bring-up time on future designs
• Raise the technical bar across the verification team by mentoring engineers and sharing hard-won lessons from complex bring-ups
• Contribute to the quality and reputation of Synopsys IP, which directly affects customer trust and product adoption
• Help define what "done" means for verification, ensuring that coverage, corner cases, and compliance are never compromised under schedule pressure

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8 to 10+ years of hands-on ASIC or SoC verification experience
• Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs
• Strong proficiency in SystemVerilog and UVM, including building testbenches, writing assertions, and developing verification IP
• Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture
• Experience using simulation tools such as VCS, ModelSim, Xcelium, or equivalent in a regression and debug workflow
• Demonstrated ability to drive functional coverage closure and deliver fully verified IP on schedule
• Experience with HBM2, HBM3, DDR4, DDR5, LPDDR4, or LPDDR5 is a strong plus

Who You Are

• You can look at a failing test and quickly narrow down whether it is a testbench issue, a design bug, or a timing problem without burning a day in the debugger
• You push back when a test plan is too shallow or a coverage model is missing a critical scenario, and you do it in a way that helps the team get better
• You can explain a complex protocol violation to a design engineer in two sentences without losing the technical nuance
• You are comfortable working across time zones and teams, coordinating with architects in one region and design engineers in another without losing momentum
• You take ownership of the verification closure process and do not wait for someone else to tell you what needs to be done next
• You mentor junior engineers by showing them how to think through a problem, not just how to fix the immediate issue in front of them

The Team You'll Be Part Of

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next generation technologies.

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.