Principal DFT Engineer

Synopsys Inc; Bengaluru; On-site; INR 4,200,000 - 6,500,000; Full time

Job summary

Synopsys Bangalore is seeking an experienced ASIC DFT professional to lead scan insertion and ATPG efforts. You will work with RTL and Verification to embed DFT early in designs, resolve DFT issues with Spyglass DFT, and guide a team towards robust testability and efficiency.

You will mentor junior engineers, drive continuous improvement of DFT methodologies, and contribute to AI-enabled DFT flows in a fast-paced, global environment.

Qualifications

• BS/MS in Electrical Engineering or ECE with 8+ years in relevant DFT roles.
• Experience leading a DFT team on IP projects and cross-functional collaboration.
• Proven DFT expertise including scan insertion and ATPG for complex ASICs.
• Proficiency with Spyglass DFT and scan STA; ability to debug DFT issues across projects.

Responsibilities

• Lead and drive execution of scan insertion and ATPG flows for complex IP designs with a DFT team.
• Collaborate with RTL and Verification to embed DFT requirements early in the design cycle.
• Analyze/resolve DFT issues using Spyglass DFT; ensure robust test coverage and manufacturability.
• Guide team and perform scan STA to validate timing closure and optimize testability paths.
• Use AI tools/flows for DFT tasks to improve efficiency.
• Collaborate with cross-functional teams and central DFT methodology to implement best practices.
• Contribute to automation and design-flow improvements to reduce turnaround time.

Skills

Leadership

Team leadership

Collaboration

Mentorship

Problem solving

Education

BS/MS in Electrical Engineering or Electronics & Communication

Tools

Spyglass DFT

Scan STA

AI tools for DFT

Scripting

Job description

We Are:

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are:

You are a passionate and detail-oriented ASIC DFT professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in technically leading team in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new AI tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. Your leadership abilities allow you to guide technical teams and enhance DFT methodologies, flow ensuring high-quality deliverables. You are committed to upholding Synopsys’ culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.

What You'll Be Doing:

• Lead and drive execution of scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex IP designs along with a team of talented DFT engineers.
• Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
• Analyze/resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
• Guide team/Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
• Use AI tools/flow for DFT tasks execution to improve the efficiency.
• Collaborate with cross-functional teams and central DFT methodology team to define and implement best practices for DFT methodologies and flows.
• Contribute to the continuous improvement of automation and design flows to boost efficiency and reduce turnaround time.

The Impact You Will Have:

• Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.
• Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization.
• Collaborate with a global team of experienced engineers, fostering a culture of knowledge sharing and continuous learning.
• Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.
• Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.
• Contribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.

What You'll Need:

• BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.
• Past experience of technically leading a team for DFT execution of IP projects. Experience in effective collaboration and stakeholder management with program management, design/verification and design implementation teams.
• Proven experience in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
• Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
• Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
• Some experience of using AI tools for DFT tasks and other basic tasks (script generation/usage) to automate design and test flows.
• Basic understanding of digital logic design, and verification principles is also useful.

Who You Are:

• Collaborative team player who communicates effectively across functions and cultures.
• Proactive problem solver, comfortable with ambiguity and rapid change.
• Detail-oriented and highly organized, with a commitment to delivering high-quality results.
• Inclusive and open-minded, eager to share knowledge and mentor others.
• Self-motivated and driven by curiosity, with a continuous learning mindset.

The Team You'll Be A Part Of:

You will join a dynamic and innovative front end IP team which includes design, verification and DFT sub teams within Synopsys' Engineering organization in Bangalore. The DFT team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.