PMIC Design Verification Lead (Sr Staff Engineer)

QUALCOMM, Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks an experienced Digital Verification Lead for PMIC IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. You will lead digital verification activities across RTL, firmware, and mixed-signal IPs with strong SystemVerilog/UVM expertise.

Collaboration with international teams and mentoring juniors is expected. Candidates should have 10+ years of ASIC design/verification experience and a proven track record delivering high-quality,

Qualifications

• Bachelor's degree with 6+ years of ASIC design/verification experience.
• Master's degree with 5+ years of ASIC design/verification experience.
• PhD with 4+ years of ASIC design/verification experience.

Responsibilities

• Lead digital verification for PMIC IPs, ASICs and chipsets.
• Collaborate with international teams from system definition to launches.
• Develop test plans and UVM-based test benches, close coverage.
• Debug complex SOCs, firmware and sequencers.

Skills

ASIC design

Verification

UVM/SV

SystemVerilog

Python scripting

UVM

SystemVerilog

Scripting

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

SystemVerilog

UVM

Python

Perl

Job description

## Company:

Qualcomm India Private Limited

## Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Digital Verification Lead (Senior Staff Engineer) for PMIC IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions.

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the invention age and this is where you come in.

As a Digital Verification Sr. Staff Engineer you will be leading digital verification for next gen PMIC technologies, Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G/6G power (mmW, envelope tracking, high-performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

• Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.
• Digital Verification aspects include all stages of the verification process, from test planning, UVM-compliant test-bench architecture, constrained random stimulus creation, score-boarding and coverage closure.
• Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus.
• Work includes debugging complex systems including SOCs, firmware, embedded sequencers.
• Position includes IP or chip digital DV ownership including task planning and project risk mitigation.
• Work in a dynamic team environment with an aggressive schedule towards metrics-based high-quality target.
• Experience in leading a team is a plus.

Preferred Qualifications

• Strong troubleshooting skills across ASIC systems disciplines (digital RTL, Firmware, analog behavioral models)
• Experience in writing Test Plans independently, planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage
• Strong communication and organizational skills
• Strong process-oriented mindset.
• Expert-level System Verilog Programming
• Advanced UVM/SV (Universal Verification Methodology using System Verilog)
• Python or Perl scripting

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field. Masters preferred
• 10+ years ASIC design, verification, or related work experience

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