LPDDR IP Design Engineer

Synopsys Inc; Bengaluru; In loco; INR 3.500.000 - 5.200.000; Tempo pieno

Descrizione del lavoro

Synopsys Inc. in Bengaluru, India invites a Sr. Staff ASIC Digital Design Engineer to lead DDR PHY IP development from design specification to productization, coordinating with cross‑functional teams to deliver LPDDR PHY IP solutions.

You will architect LPDDR PHY IP using Verilog and SystemVerilog, run simulations with Verification, Timing, DFT and Power teams, fix lint/CDC issues, and improve design flows, aiming for high performance and efficiency.

Competenze

• BS in Electrical Engineering and a minimum of 8 years of experience in complex technical development.
• Experience with synthesizable Verilog and SystemVerilog design concepts, coding, and implementation.
• Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques.
• Exhibit excellent communication skills and be self-motivated.
• Understanding of memory and memory PHY architecture is a plus.

Mansioni

• In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.
• Designing and micro‑architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification
• Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members
• Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues
• Maintain and improve design automating flow and process

Conoscenze

Verilog

SystemVerilog

Front-end design flows

Communication skills

Memory/PHY architecture

Formazione

Bachelor's in Electrical Engineering

Descrizione del lavoro

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the‑art design market with the world’s most advanced technologies for chip design and software security.

LPDDR PHY IP is a staple of the mixed‑signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next‑generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high‑performance, high‑bandwidth, low‑latency and low‑power products.

We are looking for Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world‑class market‑leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.

Job Description

In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.

Designing and micro‑architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification

Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members

Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues

Maintain and improve design automating flow and process

Required Skills

BS in Electrical Engineering and a minimum of 8 years of experience in complex technical development

Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation

Experience with front‑end design flows such as linting, synthesis, timing investigation and closure, cross‑domain clocking, DFT, and power optimization techniques

Exhibit excellent communication skills and be self‑motivated

Understanding of memory and memory PHY architecture is a plus