Lead Memory Layout Engineers

ACL Digital; Bengaluru; On-site; INR 400,000 - 900,000; Full time

Job summary

ACL Digital seeks a seasoned Lead Memory Layout Design Engineer to drive layout execution, floorplanning, and optimization for high-performance memory architectures across advanced nodes. You will lead a team of layout engineers and partner with circuit design and SOC teams to deliver high-yield physical deliverables.

The role requires 7+ years in memory layout with 2+ years in a technical lead role, strong Cadence Virtuoso and Calibre skills, and expertise in sub-7nm nodes.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 7+ years of hands‑on memory layout design experience with 2+ years in a technical lead role.
• Deep understanding of layout challenges in sub-7nm process nodes (FinFET / GAA / N3 / N2).
• Hands‑on mastery of Cadence Virtuoso (VXL/EXL) and Siemens Calibre physical verification tools.
• Proficiency in SKILL, TCL, or Python for layout automation and flow efficiency.
• Excellent problem-solving, project management, and cross-site communication skills.

Responsibilities

• Lead, mentor, and review memory layout engineers; establish layout guidelines and quality flows.
• Execute cell/block/array-level floorplanning optimizing area, power, and pitch in memory architectures.
• Drive complete layout verification closures including DRC/LVS/ER C/EM/IR across advanced nodes.
• Collaborate with circuit, CAD, and SOC teams on timing, power, and cell-pitch constraints.
• Manage delivery schedules and milestones for memory macros from concept to tape-out.

Skills

Memory Layout

Technical Leadership

Floorplanning

Physical Verification

Scripting

Cadence Tools

Education

Bachelors or Masters in Electrical Engineering/Microelectronics

Tools

Cadence Virtuoso (VXL/EXL)

Siemens Calibre

Job description

Role Title: Lead Memory Layout Design Engineer

Location: Bangalore and Hyderabad

Employment Type: Full-time

Experience Level: 8years to 20 Years

Seniority Level: Mid-Senior / Lead

About the Role

We are seeking an experienced Lead Memory Layout Design Engineer to drive physical layout execution, floorplanning, and optimization for high-performance memory architectures (SRAM, Register Files, CAM, Compiler Memories, or High-Bandwidth Memory). In this technical leadership role, you will lead a team of layout engineers, collaborate closely with circuit design and SOC integration teams, and ensure high-yield, high-density physical deliverables on cutting-edge advanced nodes (7nm, 5nm, 3nm, and below).

Key Responsibilities

• Technical Leadership: Lead, mentor, and review the work of memory layout design engineers while establishing layout guidelines, methodology improvements, and quality control flows.
• Floorplanning & Architecture: Execute cell-level, block-level, and array-level floorplanning, optimizing for area, power, performance, and pitch alignment in custom memory architectures.
• Physical Verification: Drive complete physical verification closures, including DRC, LVS, ERC, Antenna, and EM/IR (Electro-Migration / IR Drop) analysis across advanced process nodes.
• Cross-Functional Collaboration: Partner with circuit design, CAD, and SOC integration teams to align on timing, power requirements and cell-pitch constraints.
• Project Execution: Manage delivery schedules, layout floorplans, and milestones for memory compilers or custom memory macros from concept to tape-out.

Qualifications & Skills

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.
• Experience: 7+ years of hands‑on memory layout design experience with at least 2+ years in a technical lead role.
• Advanced Node Expertise: Deep understanding of layout challenges in sub-7nm process nodes (FinFET / GAA / N3 / N2).
• EDA Tool Proficiency: Hands‑on mastery of Cadence Virtuoso (VXL/EXL) and Siemens Calibre physical verification tools.
• Scripting Skills: Proficiency in SKILL, TCL, or Python for layout automation and flow efficiency.
• Soft Skills: Excellent problem-solving capabilities, project management skills, and clear communication across multi-site teams.

Preferred Qualifications

• Experience with memory compilers (SRAM/ROM/DPRAM) or emerging memory types (HBM, MRAM, RRAM).
• Direct experience with foundry design rules (TSMC, Samsung, Intel Foundry) for advanced nodes.

About ACL Digital | An ALTEN Group company

Founded: 1992

ACL Digital - ALTEN is 3rd Largest Engineering services company in the world

We are now “Great Place to work certified”

Acquired Si2chip Technologies ,Wafer Space Semiconductor & Coqube semiconductor

47,200+ Employees from 75 nationalities

ACL Digital is a design-led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start‑ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi‑cultural and transnational talent and as part of the ALTEN Group comprising over 50000+ employees spread across more than 30 countries, it promotes a collaborative knowledge-building environment.

Digital Experience, Product Innovation, Technology IT Consulting, Business Consulting Solutions, IT Service Provider, Business Analytics, Operations Consulting, Digital Transformation Consulting, SAP Oracle Netsuite, Networking and Telecom, Embedded and Semiconductor, Life Sciences, Healthcare, Product Innovation & Engineering, Professional Services, and Enterprise Application

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