Lead Full chip EM/IR analysis Engineer

Advanced Micro Devices, Inc.; Osman Nagar; On-site; INR 4,000,000 - 6,000,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices, Inc. is seeking an experienced EMIR/Power signoff engineer to lead EMIR closure for IP and full-chip SOCs. The role emphasizes collaboration across global teams, analysis of IR drop, and innovative problem solving within dynamic processor architectures.

The ideal candidate has 7–10 years of experience, strong scripting skills, and proficiency with signoff and PD/DFx tools. On-site work in India with competitive AMD benefits is offered.

Qualifications

• Minimum 7 to 10 years of relevant work experience.
• Expertise in Synthesis, ICC2/FC Physical Design flows/methodologies or equivalent tools.
• Expertise in Signoff tools like Redhawk_Sc, Voltas on EMIR, PT-PX for Power signoff and Primetime for Timing.
• Should have worked as a go-to person or technical lead for at least a few full chip projects.
• Strong technical leadership with mentoring capabilities for design engineers.
• Strong interpersonal skills and ability to collaborate across geos.
• Solid scripting experience in Shell, Python, Perl, TCL, UNIX and debugging legacy scripts.
• Must be using AI technologies in day-to-day problem solving.

Responsibilities

• EMIR closure at Tile/Partition/Subsystem/SOC level on a node.
• Drive Power and EMIR closure for design blocks and full-chip integration.
• Align EMIR analysis phases with PD milestones.
• Ensure compliance with signoff limits provided by SIPI team for the technology node.
• Analyze EMIR violations and propose implementation choices.
• Familiarity with DFx and scan architecture for EMIR considerations.
• Define EMIR signoff strategy including IR drop and electromigration analysis.
• Review floorplan, clocking, and bus structures for IR hotspots.
• Coordinate bump allocation and power rail alignment with integration teams.
• Ownership of EMIR Flow and Signoff.
• Collaboration and Coordination across teams.

Skills

EMIR

Power signoff

IR drop analysis

Scripting

AI technologies

Education

Bachelor's or Master's in Electrical Engineering

Tools

ICC2/FC (Fusion Compiler)

Redhawk_Sc

Voltas

Primetime

Fusion Compiler

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC

THE PERSON:

The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node
• Drive Power and EMIR closure for design blocks and full-chip integration.
• Align EMIR analysis phases with PD milestones .
• Ensure compliance with signoff limits provided by SIPI team for given technology node
• Ability to analyze EMIR violations and propose implementation choices.
• Familiarity with DFx and scan architecture for EMIR considerations
• Technical Leadership
  • • Define EMIR signoff strategy, including IR drop and electromigration analysis.
    • Review floorplan, clocking, and bus structures for IR hotspots.
    • Coordinate bump allocation and power rail alignment with integration teams.
• Ownership of EMIR Flow & Signoff
• Collaboration & Coordination

PREFERRED EXPERIENCE:

• • Minimum 7 to 10years of relevant work experience.
• Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
• Expertise in Signoff tools like Redhawk_Sc, Voltas on EMIR, PT-PX for Power signoff and Primetime for Timing
• Should have worked as a go to person or technical lead for at least few full chip projects.
• Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
• Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
• Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.
• Must be using AI technologies in day to day problem solving

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Electrical Engineering

#LI-SR4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.