Functional Verification Lead

AMD; Hyderabad; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

AMD Hyderabad is seeking an SMTs Engineer to provide technical leadership and hands-on verification across high-speed memory controllers, including DDR5/6 and UCIe IPs. The role demands deep experience in UVM/OVM, SystemVerilog test benches, and advanced verification tools, with proven team leadership abilities.

You will plan and drive verification strategies, coordinate with design teams, and push for rigorous verification closure and delivery to programs while maintaining strong communication.

Qualifications

• BS w/ 12+ yrs or MS w/ 11+ yrs or PhD w/ 9+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
• Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs.
• Proven track record in technical leadership of teams of 9+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.

Responsibilities

• Provide technical leadership and contribution on high-speed Memory Controller IP Verification.
• Design, develop and use simulation and/or formal verification environments to prove functional correctness of DDR5/6 RLD3 Memory Controller and UCIe IP designs.
• Lead verification strategy, plans, and execution for high-performance IPs and SOCs.
• Coordinate with Memory Controller design teams to improve product quality and delivery to programs.

Skills

Memory verification

UVM/OVM

SystemVerilog

Leadership

Team management

Debug skills

Education

BS/MS/PhD in EE/CE/CS

Tools

Synopsys VCS

Cadence IES

Jasper

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

SMTS Engineer to provide technical leadership and contribution on high speed Memory Controller IP Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of DDR5/6 RLD3 Memory Controller, UCIe IP designs.

The ideal candidate is one who has a proven track record on driving strategies and successful verification execution high performance IPs and/or SOC designs.

Require hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, UCIe. Requires strong understanding of current memory controller protocols and calibration board skew and jitter modeling.

With a proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs.

Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.

#LI-NR1

Qualifications:

• BS w/ 12+ yrs or MS w/ 11+ yrs or PhD w/ 9+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
• Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs.
• Proven track record in technical leadership of teams of 9+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
• Hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR. Requires strong understanding of current memory controller protocols and calibration specification, board skew and jitter modeling.
• Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
• Familiarity with verification management tools as well as understanding of database management particularly as it pertain to regression management.
• Experience with formal property checking tools such as Cadence , Jasper and Synopsys is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
• Prior experience with silicon debug at the tester and board level, is a plus.

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.