FPGA Verification Engineer M/F

Safran Group; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Safran Electronics & Defense in Asia, India, seeks an FPGA Verification Engineer M/F to join the actuation‑systems team in Bengaluru (Kundalahalli). The role focuses on requirement-based testing for FPGA verification using SystemVerilog and UVM within a DO‑254 framework.

Responsibilities include building test suites, developing robust test benches, collaborating with design and architecture teams, and mentoring junior engineers.

Qualifications

• Bachelor's/Master's degree in Engineering (ECE, VLSI)
• 4-8 years of industry experience in ASIC/FPGA verification
• Hands-on experience in SV UVM verification environment from scratch
• Experience with Questa or Modelsim or similar tools
• Experience in DO-254 verification process
• Exposure to test plan generation and test bench writing
• RTL Design experience in VHDL is a plus
• Excellent oral and written communication skills

Responsibilities

• Develop test suites and test environments using SystemVerilog UVM
• Create self-checking test-benches to meet verification criteria and coverage
• Participate in requirement validation and reviews
• Handle protocols: PCIe, SPI, ARINC 429, MIL-STD-1553, image processing
• Collaborate with verification, architecture, applications and design teams
• Develop/update verification environment for block and system level
• Assist design team in debugging and coverage gap analysis
• Verify structural and functional coverage of tests
• Apply SV/UVM and scripting skills (PERL) to debugging
• Provide technical guidance to junior engineers

Skills

SystemVerilog UVM

Code coverage

Debugging

RTL verification

SystemVerilog

Education

Bachelor's/Master's in ECE/VLSI

Tools

Questa

ModelSim

DOORS

Jama

Job description

FPGA Verification Engineer M/F

Vacancy details

General information

Entity

Safran is an international high-technology group operating in the fields of aerospace (propulsion, equipment and interiors), space and defense. Its mission is to contribute sustainably to a safer world, where air transport becomes ever more environmentally friendly, comfortable and accessible. Present on every continent, the Group employs 110,000 people and generated €31.3 billion in revenue in 2025. Safran holds, either independently or through partnerships, leading global or European positions in its markets.

Safran was ranked second in the Aerospace & Defense sector in TIME magazine's "World's Best Companies 2025" ranking.

Safran Electronics & Defense is an international company with more than 19,000 employees who bring together expertise and team spirit to design high-technology solutions for the aerospace, defense and space sectors. By combining human and technological intelligence, the company develops products and services for both civil and military customers, operating on land, at sea, in the air and in space.

Reference

2026-170650

Position description

Domain

Research, design and development

Job field / Job profile

Electronics and automation - FPGA

Job title

FPGA Verification Engineer M/F

Employment type

Permanent

Part time / Full time

Full-time

Job description

Description of the Role:

In this role as a Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards requirement-based testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.

FPGA JD:

Primary Responsibilities:

1. Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals.
2. Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage.
3. Participate in requirement validation and requirement review.
4. Protocols - PCIe, SPI, ARINC 429, Mil 1553, Image processing.
5. Actively participate in a team environment, working with verification, architecture, applications, and design teams to develop comprehensive verification plans and address issues.
6. Verification environment development/update for block level and system level.
7. Work closely with design team on design de-bugging, coverage gap analysis etc.
8. Verify structural and functional coverage of module and system level test suite.
9. Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.
10. Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
11. Technical guidance to the junior engineers on verification tasks.

Candidate skills & requirements

Qualifications:

• Bachelor's/Master's degree in Engineering (ECE , VLSI)
• 4-8 years of Industry experience with experience in development, integration & verification of ASIC/FPGA.
• Hands on experience in developing SV UVM verification environment from scratch.
• Hands on experience with Questa or Modelsim or similar advanced simulation tools.
• Hands on experience in DO-254 verification process.
• Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently.
• Exposure to test plan generation, test bench writing, simulation of designs.
• Experience in RTL Design using VHDL, Complete FPGA development flow and FPGA verification using VHDL will be a plus.
• Experience in DOORS/Jama will be a plus.
• Excellent oral and written communication skills

Position location

Job location

Asia, India

City (-ies)

Kundalahalli, Bangalore

Candidate criteria

Minimum education level achieved

Bachelor's Degree

Minimum experience level required

More than 5 years