FPGA Silicon Validation Engineer

Altera; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Altera in Bengaluru, India seeks an experienced FPGA post-silicon validation lead. You will own validation, plan PVT and non-PVT tests, and drive automation with Python, Tcl, and C to scale coverage and accelerate issue resolution.

Ideal candidates have 5–8 years in HW or FPGA validation, strong debugging skills across silicon, firmware, and boards, and a proven ability to mentor juniors while delivering robust validation results.

Qualifications

• 5–8 years experience in post-silicon / FPGA / HW validation or protocol bring-up
• Proven ownership of design bring-up and HW validation through production-quality outcomes
• Hands-on PVT and regression planning, execution, and fail analysis
• Strong HW knowledge plus automation in Python, Tcl, and C

Responsibilities

• Own validation covering PVT and non-PVT (functional, feature, system)
• Define, maintain, and scale regression suites (content, automation, overnight runs)
• Architect and deliver design/test automation in Python, Tcl, and C
• Use RTL and on-chip debug to root-cause failures across HW, timing, firmware, and board
• Set test plans, coverage expectations, and validation exit criteria
• Mentor junior engineers; review bring-up quality, regression health, and documentation
• Represent validation in milestone reviews and technical escalations
• Mentor juniors or lead a validation workstream

Skills

FPGA validation

Post-silicon validation

Debugging

Team mentoring

Education

B.E./B.Tech/M.S. in ECE/EE/Computer Engineering

Tools

Python

Tcl

C

Verilog/SystemVerilog

Job description

Job Description

Own FPGA post-silicon validation for assigned domains/products: lead design bring-up, plan and execute PVT and non-PVT testing including regression, build scalable design/test automation, and drive debug to closure. High individual ownership with strong cross-team collaboration (DV, IPSS, Customer Support).

Key Responsibilities

• Own validation covering PVT (corners, voltage/temp sweeps, fmax/margin, stress) and non-PVT (functional, feature, system)
• Define, maintain, and scale regression suites (content, automation, overnight runs, fail triage, exit criteria)
• Architect and deliver design/test automation in Python, Tcl, and C
• Use RTL and on-chip debug to root-cause failures across HW, timing, firmware, and board
• Set test plans, coverage expectations, and validation exit criteria for assigned work
• Defines and delivers continuous improvement of silicon validation environment and methodologies
• Debugs and resolves silicon bring up issues, documents the solutions, troubleshoots, and debugs silicon from prototype to production.
• Partner with DV, IPSS, and Customer Support on correlation, integration, and customer/field issues
• Mentor junior engineers; review bring-up quality, regression health, and documentation
• Represent validation in milestone reviews and technical escalations
• Mentored juniors or led a validation workstream

Preferred Depth

• Ethernet
• ANLT
• PTP
• D-PHY
• CPRI
• JESD
• SerialLite
• DP
• HDMI
• SATA
• SAS Thermal chamber / shmoo / margin characterization

Board/schematic literacy; basic SI/PI for high-speed links

Soft Skills

• Self-motivated technical owner for domain/product validation outcomes
• Strong individual contributor who delivers with limited oversight
• Effective team collaborator across DV, IPSS, Customer Support, and design

Qualifications

• B.E. / B.Tech / M.S. in ECE, EE, Computer Engineering, or related 5–8 years experience in post-silicon / FPGA / HW validation or protocol bring-up, aligned to Grade 6 / 7
• Proven ownership of design bring-up and HW validation through production-quality outcomes
• Hands‑on PVT and regression planning, execution, and fail analysis
• Strong HW knowledge plus automation in Python, Tcl, and C
• Solid RTL debug ability (Verilog/SystemVerilog or VHDL)
• FPGA tool and lab proficiency (JTAG/debug, scopes/analyzers, protocol tools as applicable)
• Demonstrated collaboration with DV, IP/integration (IPSS or equivalent), and customer‑facing teams
• Clear technical writing for plans, bugs, and status
• Emulation or pre-si to post-si correlation experience

Job Type

Regular Shift: Shift 1 (India)

Location

Primary Location: Bengaluru, Karnataka, India

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.