Embedded AI Architecture and Systems Engineer

Qualcomm; Hyderabad; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Qualcomm in Hyderabad seeks an experienced engineer to analyze, design, and optimize ML kernels on ML hardware accelerators for power, performance, and area efficiency in value-tier chipsets. You will benchmark ML subsystems, identify bottlenecks, and propose solutions for throughput gains.

Collaborate with hardware and software teams to enhance ML HW microarchitecture, memory hierarchy, and dataflow. Develop performance models for AI workloads on embedded platforms and prototype new features

Qualifications

• Experience in DSP architecture and embedded NPU design.
• Proven ability in performance analysis, benchmarking and optimization on embedded processors (DSP, ARM, RISC-V, NPU).
• Strong programming skills in Embedded C/C++, Python.
• Experience with embedded platforms and RTOS, HW/SW co-design.
• Expertise in fixed-point and floating-point implementations for ML workloads.
• Excellent communication and teamwork, able to work with global teams.

Responsibilities

• Analyze, design, and optimize ML kernels on ML HW accelerator for performance, power, and area efficiency in value tier chipsets.
• Conduct architectural analysis and benchmarking of ML subsystems, identifying bottlenecks and proposing solutions for improved throughput and efficiency.
• Collaborate with hardware and software teams to define and implement enhancements in ML HW microarchitecture, memory hierarchy, and dataflow.
• Develop and validate performance models for AI workloads, including signal processing and ML inference, on embedded platforms.
• Prototype and evaluate new architectural features for ML HW, including quantization, compression, and hardware acceleration techniques.
• Support system-level integration, performance testing, and demo prototyping for commercialization of optimized ML solutions.
• Document architectural analysis, optimization strategies, and performance results for internal and external stakeholders.

Skills

DSP architecture

Embedded NPU design

Low-power AI systems

Performance analysis

Benchmarking

Embedded C/C++

Python

RTOS

HW/SW co-design

Fixed-point/FP arithmetic

ML/AI workloads

Communication & teamwork

Tools

Embedded platforms

Real-time OS skills

Hardware/software co-design tools

Job description

Role & responsibilities

• Analyze, design, and optimize Machine learning kernels on ML HW accelerator for performance, power, and area efficiency in value tier chipsets.
• Conduct architectural analysis and benchmarking of ML subsystems, identifying bottlenecks and proposing solutions for improved throughput and efficiency.
• Collaborate with hardware and software teams to define and implement enhancements in ML HW microarchitecture, memory hierarchy, and dataflow.
• Develop and validate performance models for AI workloads, including signal processing and ML inference, on embedded platforms.
• Prototype and evaluate new architectural features for ML HW, including quantization, compression, and hardware acceleration techniques.
• Support system-level integration, performance testing, and demo prototyping for commercialization of optimized ML solutions.
• Document architectural analysis, optimization strategies, and performance results for internal and external stakeholders.

Preferred candidate profile

• Solid background in DSP architecture, embedded NPU design, and low-power AI systems.
• Proven experience in performance analysis, benchmarking, and optimization on any embedded processors (DSP, ARM, RISC-V, NPU).
• Strong programming skills in Embedded C/C++, Python
• Experience with embedded platforms, real-time operating systems, and hardware/software co-design.
• Expertise in both fixed-point and floating-point implementation, with a focus on ML/AI workloads.
• Excellent communication, presentation, and teamwork skills; ability to work independently and across global teams.
• Strong fundamentals of Power modeling and Power analysis