Digital Verification Engineer

Strategic Micro Systems of NJ, LLC.; Greater Noida, Bengaluru; On-site; INR 300,000 - 600,000; Full time

Job summary

STMicroelectronics invites an experienced verification professional to lead ARM-based SoC verification activities. You will drive verification planning, test bench development, and advanced UVM-based verification across IP, subsystem, and full SoC levels.

The role emphasizes debugging, stimulus generation, and assertion-based verification, with familiarity in low power verification and EDA tool flows. Strong RTL understanding is required.

Qualifications

• 12-15 years of experience.
• Lead complete ARM based SoC level verification activities.
• Verification planning, reviewing, architecture definition, verification test bench development and implementation.
• Development of verification test bench components such as drivers, monitors, response checkers and advanced UVM VIPs.
• Development of direct and constrained-random stimulus; RTL analysis and coverage results.
• Strong debugging, failure re-creation and root cause analysis.
• Gate level simulations (unit delay, SDF) and its debugging.
• Test pattern debugging and verification for automatic testers.
• Continuous improvement of verification methods/tools/flows with EDA partners; low power verification using CPF/UPF desirable.
• Assertion-based verification knowledge is a plus.

Responsibilities

• Responsibilities encompass development of verification test bench, verification components, test cases for simulation, debugging failures and creating simulation cases for various studies.
• Work with cutting-edge verification methodologies on standalone IPs, subsystem level and SoC level.

Skills

ARM SoC verification

UVM

SystemVerilog

VHDL/Verilog

C language

PERL/Python UNIX/LINUX

DUT/RTL debug

Scripting proficiency

Xcelium/VCS/Questasim

AMBA AXI/AHB/APB

Debug and root cause analysis

Gate level sim with SDF

Education

Bachelor/Master in Electronics/CS

Tools

Xcelium

VCS

Questasim

VManager

UTL/Verdi (debug)

Job description

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

Drive to “zero-defect”. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting‑edge verification methodologies on standalone IPs, Subsystem level and SoC level.

Responsibilities include but not limited:

• 12 - 15yrs of experience
• Lead complete ARM based SoC level Verification activities
• Verification planning, reviewing, architecture definition, Verification test bench development and implementation
• Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs.
• Development of direct and constrained-random stimulus; Understanding and analysis of RTL code, functional, assertion coverage results;
• Strong skills in debug, failure re-creation and root cause analysis
• Gate level simulations (unit delay, and with SDF annotated) and its debugging
• Test pattern debugging and testing for verification and automatic testers
• Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost effective and innovative verification techniques
• Low Power intent verification using CPF, UPF will be desirable.
• Assertion based verification will be a plus
• Qualification: Bachelors/Masters in Electronics/Computer Science
• VHDL/Verilog, System Verilog, C language
• OVM/UVM, Class based verification methodologies
• Deep Understanding of multi core based SoC architecture
• AMBA – AXI, AHB, APB bus protocols
• NIC/FlexNOC interconnect with Cache coherency, DDR3/LPDDR4/Flash memory subsystem architecture knowledge
• Communication Protocols like CAN, Graphics/Multimedia/Networking IPs like PCIe, MIPI, GPU, Ethernet, USB, DSP, Image/Computer Vision, RADAR processing
• Scripting proficiency - PERL, Python, UNIX/LINUX
• Simulation tools like – Xcelium/VCS/Questasim. Planning and regression tools like VManager
• Exposure to any of defect and version management tool

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

To discover more, visit st.com/careers.