Digital Design Engineer – AI Accelerators

STMicroelectronics; Greater Noida; Sur place; INR 1 800 000 - 2 800 000; Plein temps

Résumé du poste

STMicroelectronics is seeking a Digital Design Engineer in India to contribute to the AI accelerator development roadmap. You will work across hardware design, modeling, architecture exploration, implementation, and verification to deliver high-throughput datapaths.

The role requires a Bachelor's or Master's in Electrical or Computer Engineering, 3–4 years of RTL design and microarchitecture experience, and strong SystemVerilog/Verilog skills with familiarity in EDA tools.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3–4 years of experience in RTL design and microarchitecture (ASIC or high-end FPGA).
• Strong expertise in SystemVerilog/Verilog.
• Deep understanding of pipelined datapath design, memory hierarchy, and high-performance digital systems.
• Familiarity with EDA tools such as Questa, SpyGlass, Design Compiler, and STA tools.

Responsabilités

• Compute datapath design and microarchitecture for neural network primitives.
• HW/SW co-design and performance modeling with compiler and ML teams.
• RTL development & verification using SystemVerilog/Verilog; develop testbenches and debug blocks.
• Physical implementation support: lint, synthesis, and timing closure with physical design teams.

Connaissances

RTL design

SystemVerilog/Verilog

microarchitecture

memory hierarchy

EDA tools

Formation

Bachelor's or Master's in Electrical/Computer Engineering

Outils

Questa

SpyGlass

Design Compiler

STA tools

Description du poste

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today. When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world. Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential. Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

About the Role

We are looking for a Digital Design Engineer to join our R&D team and contribute to our AI accelerator development roadmap. The role involves work across hardware design, modeling, specification, architecture exploration, implementation, and verification.

Key Responsibilities

• Compute Datapath Design & Microarchitecture
  • Architect and implement high-throughput compute datapaths for neural network primitives
  • Integrate compute blocks with SRAM banks, register files, and external memory interfaces (e.g AXI)
• HW/SW Co-Design & Performance Modeling
  • Collaborate with compiler and ML teams to map models onto hardware efficiently
• RTL Development & Verification Collaboration
  • Implement RTL in SystemVerilog/Verilog with a focus on modular, parameterized, and reusable design.
  • Perform verification tasks on the blocks designed, including testbench support, functional checks, and debug
  • Work closely with DV teams to define coverage for complex dataflow scenarios.
• Physical Implementation Support
  • Drive lint, synthesis, and STA flows.
  • Collaborate with physical design teams to ensure timing closure for deeply pipelined and high-frequency compute blocks.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3--4 years of experience in RTL design and microarchitecture (ASIC or high-end FPGA).
• Strong expertise in SystemVerilog/Verilog.
• Deep understanding of pipelined datapath design, memory hierarchy, and high-performance digital systems.
• Familiarity with EDA tools such as Questa, SpyGlass, Design Compiler, and STA tools.

Preferred / Bonus Qualifications

• Experience designing AI/ML accelerators
• Proficiency in Python for modeling, testbench development, or hardware generation (e.g., Cocotb, PyRTL).
• Knowledge of quantization techniques and low-precision formats.
• Familiarity with ML frameworks (PyTorch, TensorFlow) and compiler stacks.

R&D Mindset & Collaboration

• Demonstrate a strong research-oriented mindset with the ability to explore ambiguous problem spaces, prototype new ideas, and iterate quickly based on empirical results.
• Be self-motivated, flexible, and adaptable in a dynamic R&D environment where priorities and technical directions may evolve.
• Show curiosity, ownership, and initiative in driving topics forward from concept to implementation.
• Contribute across multiple phases of development, from specification and architectural exploration to implementation and verification.
• Collaborate effectively with multidisciplinary teams

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction.

ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance. At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. To discover more, visit st.com/careers.