DFT Technical Architect_Visakhapatnam

Eximietas Design; Visakhapatnam; On-site; INR 900,000 - 1,800,000; Full time

Job summary

Eximietas Design in Visakhapatnam is seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.

The role requires hands-on experience with Tessent, TestMAX/TetraMAX, or Modus, and expertise in ATPG, DRC analysis, and pattern retargeting. You will collaborate with Design, Verification and Physical Design teams to deliver sign-off.

Qualifications

• Experience with ATPG simulations and netlist handling.
• Hands-on experience in block- and SoC-level pattern retargeting.
• Knowledge of ICL and PDL standards.

Responsibilities

• End-to-end ownership of the DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification and Physical Design teams.
• DFT sign-off ownership and deliverables.

Skills

End-to-End DFT Flow Ownership

Scan Insertion, EDT & OCC

ATPG, DRC Analysis & Coverage Closure

SoC Integration & Pattern Retargeting

MBIST, IJTAG & JTAG Implementation

DFT Sign-off Activities

Tools

Tessent

TestMAX/TetraMAX

Modus

Job description

Locations

• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.

Key Skills:

• End-to-End DFT Flow Ownership.
• Scan Insertion, EDT & OCC.
• ATPG, DRC Analysis & Coverage Closure.
• SoC Integration & Pattern Retargeting.
• MBIST, IJTAG & JTAG Implementation.
• DFT Sign-off Activities.

Tools Expertise:

Preferred Skills:

• Streaming Scan Network (SSN).

Core Responsibilities:

• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.

Technical Requirements:

• Strong experience in ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.
• Strong understanding of ICL and PDL standards.
• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.

Interested candidates can share their updated resume at:

Referrals are highly appreciated. Please share within your network.

Best Regards,

Associate VLSI Manager – Talent Acquisition | Visakhapatnam