DFT Lead - ATPG

AMD; Bengaluru Urban; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

AMD’s Radeon Technologies Group in Bengaluru seeks an SMTS Silicon Design Engineer to advance front-end design/integration, collaborating with architecture, IP design, physical design and product engineers to achieve first pass silicon success.

The role emphasizes rigorous DFT verification, stress on accurate problem-solving, and close teamwork to deliver high-quality silicon for AI, data centers and embedded applications.

Qualifications

• Understanding of Design for Test methodologies and DFT verification experience.
• Experience with scan, ATPG, and corresponding verification methods.
• Strong problem-solving and communication skills.

Responsibilities

• Implementation and verification of DFT architecture and features.
• Scan insertion and ATPG pattern generation.
• ATPG patterns verification with gate-level simulation.
• Test coverage and test cost reduction analysis.
• Post silicon support to ensure successful bring up and yield learning.

Skills

DFT verification

JTAG 1149.x

Scan insertion

ATPG

Verilog RTL

Perl/Shell scripting

VCS

Education

Bachelor's or Masters in Computer/Electrical Engineering

Tools

Mentor TestKompress

Synopsys Tetramax/DFTMAX

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

SMTS SILICON DESIGN ENGINEER

THE ROLE:

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Implementation and verification of DFT architecture and features

• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

PREFERRED EXPERIENCE:

• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-RR1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.