CUDA Kernel Engineer

Nava; Bengaluru; On-site; INR 1,500,000 - 2,600,000; Full time

Job summary

Nava in Bengaluru, Karnataka, seeks a CUDA developer to design and optimize high-performance kernels for NVIDIA Ampere and Hopper architectures. You will write CUDA C++, profile memory traffic and bottlenecks, and collaborate with ML and HPC teams to translate requirements into scalable GPU code.

The role emphasizes fused operations, shared memory tiling, and warp-level primitives, with maintainable, well-documented kernels.

Qualifications

• Proficient in CUDA C++ and GPU architecture concepts.
• Experience with Nsight Compute for profiling and optimization.
• Hands-on knowledge of NVIDIA Ampere/Hopper architectures and memory hierarchy.
• Ability to apply memory bandwidth optimizations and warp-level techniques.
• Experience with nvcc and PTX/SASS basics.

Responsibilities

• Design, write, and optimize high-performance CUDA kernels targeting NVIDIA Ampere, Hopper, and upcoming architectures.
• Profile and debug GPU memory bandwidth, occupancy, and bottlenecks using Nsight Compute, Visual Profiler, and custom instrumentation.
• Collaborate with ML and HPC teams to translate algorithmic requirements into efficient, scalable GPU code.
• Implement fused operations, shared memory optimizations, and warp-level primitives to maximize throughput under latency and memory constraints.
• Contribute to kernel library development and maintain reusable, well-documented, and performance-tested modules.
• Stay ahead of evolving CUDA toolchains, compiler flags, and architecture-specific features to continuously extract performance wins.

Skills

CUDA C++

Nsight Compute

NVIDIA GPU Architecture (Ampere/Hopper

GPU Memory Hierarchy Optimization

Warp-Level Primitives

Profiling & Performance Tuning

nvcc Compiler

PTX / SASS Assembly (Basic)

Tools

nvcc Compiler

cuDNN

cuBLAS

CUTLASS

Tensor Cores and FP8/FP16 kernels

Job description

Role & Responsibilities

• Design, write, and optimize high-performance CUDA kernels targeting NVIDIA Ampere, Hopper, and upcoming architectures.
• Profile and debug GPU memory bandwidth, occupancy, and instruction-level bottlenecks using Nsight Compute, Visual Profiler, and custom instrumentation.
• Collaborate with ML and HPC teams to translate algorithmic requirements into efficient, scalable, and portable GPU code.
• Implement fused operations, shared memory optimizations, and warp-level primitives to maximize throughput under latency and memory constraints.
• Contribute to kernel library development and maintain reusable, well-documented, and performance-tested modules.
• Stay ahead of evolving CUDA toolchains, compiler flags, and architecture-specific features to continuously extract performance wins.

Skills & Qualifications

Must‑Have

• CUDA C++
• Nsight Compute
• NVIDIA GPU Architecture (Ampere/Hopper)
• GPU Memory Hierarchy Optimization
• Warp-Level Primitives
• Profiling & Performance Tuning
• nvcc Compiler
• PTX / SASS Assembly (Basic Understanding)

Preferred

• Experience with Tensor Cores and FP8/FP16 kernels
• Familiarity with cuDNN, cuBLAS, or CUTLASS
• Contributions to open-source GPU compute projects