Compiler Engineer (GPU Backend)

OXMIQ Labs, Inc.

Hyderabad

On-site

INR 4,000,000 - 6,000,000

Full time

3 days ago
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Benefits offered by this job

Equity participation
Medical coverage
Foundational silicon work

Job summary

OXMIQ Labs, Inc. is seeking a senior compiler engineer to design and optimize compiler infrastructure for GPU-accelerated workloads, focusing on lowering pipelines, optimization passes, and code generation backends.

You will work closely with hardware teams to maximize utilization and performance on the Oxmiq IP and GPU architectures. Responsibilities include implementing segmentation and scheduling strategies, operator fusion and tiling optimizations, memory planning, and integration with

Qualifications

  • 5+ years of experience in compiler engineering, focus on GPU/NPU/AI accelerator stacks.
  • Strong proficiency in C++.
  • Hands-on experience with modern compiler frameworks like MLIR, LLVM, TVM, or IREE.
  • Experience designing or implementing compiler optimizations, scheduling, segmentation/partitioning, or lowering pipelines for GPU/NPU hardware.
  • Solid understanding of IR transformations, code generation, instruction scheduling, register allocation, vectorization, memory hierarchy optimization.
  • Familiarity with CUDA or Triton GPU programming models.
  • Understanding of GPU architecture fundamentals and performance bottlenecks.
  • Experience optimizing compiler-generated code for modern GPU/AI accelerators.
  • Strong debugging, profiling, and performance analysis skills.

Responsibilities

  • Design and implement compiler infrastructure for GPU workloads.
  • Develop and optimize passes and code generation backends.
  • Optimize segmentation and scheduling for Oxmiq hardware backend.
  • Develop compiler optimizations for fusion, tiling, memory planning, and workload partitioning.
  • Collaborate with architecture and hardware teams on performance-driven transformations.
  • Support Triton-based models, custom operator lowering, and integration with LLM frameworks such as vLLM and SGLang.
  • Optimize output for throughput, latency, memory efficiency and scalability.
  • Participate in architecture discussions, design reviews, and code reviews.
  • Support performance profiling, benchmarking, debugging, and root-cause analysis.

Skills

5+ years exp
C++
MLIR/LLVM/TVM/IREE
GPU/NPU compiler
IR transformations
CUDA/Triton
Performance profiling
Claude Code tooling

Education

B.E./B.Tech/M.E./M.Tech/MS/Ph.D. in Computer Science or related

Tools

MLIR/LLVM
TVM
Triton
IREE
Claude Code

Job description

  • Design and implement compiler infrastructure for GPU-accelerated workloads, including lowering pipelines, optimization passes, and code generation backends.
  • Develop and optimize compilation passes targeting Oxmiq hardware IP and GPU architectures.
  • Design and implement segmentation and scheduling strategies for the Oxmiq hardware backend to maximize hardware utilization, throughput, and execution efficiency.
  • Develop compiler optimizations for operator fusion, tiling, memory planning, and workload partitioning across GPU hardware.
  • Collaborate with architecture and hardware teams to translate performance requirements into efficient compiler transformations and code generation strategies.
  • Work with kernel engineers to support Triton-based programming models, custom operator lowering, and integration with modern LLM serving frameworks such as vLLM and SGLang.
  • Optimize compiler output for throughput, latency, memory efficiency, and scalability across AI workloads.
  • Participate in architecture discussions, design reviews, and code reviews.
  • Support compiler performance profiling, benchmarking, debugging, and root cause analysis.
Required Qualifications
  • 5+ years of experience in compiler engineering, with a focus on GPU, NPU, or AI accelerator software stacks.
  • Strong proficiency in C++.
  • Hands-on experience with at least one modern compiler framework such as MLIR, LLVM, TVM, or IREE.
  • Experience designing or implementing compiler optimizations, scheduling algorithms, segmentation/partitioning strategies, or lowering pipelines for GPU/NPU hardware.
  • Solid understanding of compiler concepts including IR transformations, code generation, instruction scheduling, register allocation, vectorization, and memory hierarchy optimization.
  • Familiarity with GPU programming models such as CUDA or Triton.
  • Understanding of GPU architecture fundamentals including thread execution models, memory systems, occupancy, synchronization, and performance bottlenecks.
  • Experience optimizing compiler-generated code for performance on modern GPU or AI accelerator hardware.
  • Strong debugging, profiling, and performance analysis skills.
  • Hands-on experience with Claude Code or equivalent AI-assisted software development workflows.
Preferred Qualifications
  • Experience developing compiler backends for custom AI accelerators, NPUs, or GPU IP.
  • Experience with Triton compiler internals or other high-level GPU kernel frameworks.
  • Familiarity with kernel fusion, operator tiling, graph partitioning, auto-tuning, and workload scheduling.
  • Exposure to quantization, mixed precision, sparsity-aware compilation, or memory optimization techniques.
  • Experience integrating compiler technology with LLM serving frameworks such as vLLM or SGLang.
  • Experience with performance modeling, roofline analysis, or hardware-aware optimization.
  • Contributions to open-source compiler projects such as LLVM, MLIR, TVM, Triton, or IREE.
  • Python scripting experience for compiler tooling, testing, automation, or benchmarking.
Education
  • B.E./B.Tech/M.E./M.Tech/MS/Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or a related field.

The successful candidate will work within a compact, senior team comprising compiler engineers, hardware architects, and kernel authors. A senior compiler engineer will serve as the primary technical mentor, providing direction, code review, and guidance across MLIR, LLVM backend development, and GPU code generation on production silicon.

OXMIQ offers a competitive compensation package, including base salary, equity participation, comprehensive medical coverage, and the opportunity to contribute to foundational silicon and software technology.

OXMIQ is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected characteristic.

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