ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years

Cisco Systems, Inc; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Cisco Systems, Inc in Bengaluru, India seeks an ASIC Design for Test Hardware Engineer with 4–8 years of experience to design and implement DFT features for complex ASICs. You will work on ATE, in-system test, and diagnostics, collaborating with design, verification and PD teams to integrate Test logic across the full chip flow.

The role requires knowledge of JTAG, ATPG, BScan, and EDA tools (TestMax, Tetramax, Tessent), with scripting in Tcl/Python/Perl and strong communication in a

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering with 4–8 years of experience.
• Knowledge of DFT, test and silicon engineering trends and tooling.
• Experience with JTAG, ATPG, Scan insertion, BScan, ATPG/EDA tools (TestMax/Tetramax/Tessent).
• Gate-level sim in VCS; post-silicon validation and ATE patterns (P1687).
• Scripting in Tcl, Python or Perl; strong verbal skills in a multifaceted environment.

Responsibilities

• Implement Hardware DFT features supporting ATE, in-system test, debug and diagnostics.
• Develop innovative DFT IP and integrate testability features with RTL.
• Collaborate with design, verification and PD teams to validate Test logic.
• Craft solutions and debug with minimal mentorship.

Skills

JTAG protocols

ATPG

Scan insertion

BScan

Tessent

Tetramax

TestMax

Gate-level sim

VCS

Tcl scripting

Python/Perl

Education

Electrical or Computer Engineering

Tools

TestMax

Tetramax

Tessent

VCS

Job description

Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies.

Minimum Qualifications

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-8 years of experience.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Experience with Jtag protocols, Scan insertion and ATPG, BScan
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.
• Knowledge of the latest innovative trends in DFT, test and silicon engineering.
• Experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Strong verbal skills and ability to thrive in a multifaceted environment
• Scripting skills: Tcl, Python/Perl.

Preferred Qualifications

• Test Static Timing Analysis
• Post silicon validation using DFT patterns.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.