Architect Digital Design -High Speed Memory Interface IP- HBM DDR LPDDR

Synopsys Inc; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Synopsys Inc. in Hyderabad, India, seeks an Architect Digital Design for memory interface IP (HBM/DDR/LPDDR) with 12–15+ years of ASIC experience.

You will define core memory IP architectures, drive design plans, and mentor teams across global sites, delivering silicon-ready interfaces for AI accelerators and data center processors. The role requires deep knowledge of high-speed memory protocols, RTL implementation, and AMBA interconnects, with a focus on performance, area, and power tradeoffs.

Qualifications

• Extensive hands-on ASIC digital design with memory interfaces.
• Deep knowledge of HBM, DDR, or LPDDR protocols and controller architecture.
• Proven ability to define and execute architectures from concept to RTL and silicon bring-up.
• Strong AMBA or similar interconnect knowledge and memory integration.

Responsibilities

• Define and own the digital architecture for memory controllers from high-level partitioning to RTL implementation.
• Drive design plans for memory interface blocks balancing performance, area, power, and verification.
• Collaborate with PHY teams, verification engineers, and product architects for integration and protocol compliance.
• Evaluate and select design methodologies, tools, and flows to improve quality and reduce cycle time.
• Mentor engineers on architecture decisions and RTL best practices.
• Work with customers and stakeholders to align on feature requirements, timing, and milestones.
• Review RTL, testbenches, and verification plans to catch architectural issues early.

Skills

ASIC design experience

Memory interfaces

HBM/DDR/LPDDR knowledge

RTL implementation

AMBA protocols

Design tools

Communication skills

HBM3/DDR5/LPDDR5X knowledge

Tools

Synthesis tools

Timing closure tools

Power analysis tools

Job description

Job Description:

Alternate Job Titles

• Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building memory interface IP that has to work at the bleeding edge of performance, power, and reliability. Not just meet spec, but hold up under real-world corner cases that no one thought to write down. You know that the difference between a memory controller that ships and one that gets redesigned six months later is usually an architectural decision made early, and you are the kind of architect who sees around those corners.

You think in tradeoffs. Bandwidth versus latency. Area versus configurability. What works in simulation versus what survives silicon. When someone asks if we can support a new HBM3 feature, you do not say yes or no, you say here is what it costs and here is what we get, and you have the depth to back it up with real numbers.

You have worked across HBM, DDR, LPDDR, or similar high-speed memory protocols long enough to know where the complexity lives. Maybe it is training algorithms. Maybe it is clock domain crossings. Maybe it is how you partition the PHY interface so verification does not become a nightmare. You do not need to be told what matters, you already know.

At Synopsys, you will define the architecture for memory IP that powers AI accelerators, data center processors, and mobile SoCs used by millions of people. The team is global, the problems are hard, and what you design will ship.

What You'll Be Doing

• Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy
• Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity across chip and block levels
• Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance
• Evaluate and select design methodologies, tools, and flows that improve quality, reduce cycle time, and scale across product lines
• Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces
• Work directly with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones
• Review and guide RTL, testbenches, and verification plans to catch architectural issues before they become silicon problems

The Impact You Will Have

• Your architecture decisions will define the performance ceiling and power floor for memory IP used in next-generation AI and data center chips
• You will reduce time-to-market by building memory controllers that are easier to verify, integrate, and customize across multiple product variants
• The IP you help design will ship in millions of devices, from smartphones to high-performance computing systems
• You will elevate the technical depth of the team by mentoring engineers and establishing architectural patterns that scale
• Your ability to navigate ambiguity and make sound tradeoffs will directly influence which features ship and which get deferred
• You will help Synopsys maintain its leadership position in memory IP by driving innovations in HBM3, DDR5, LPDDR5X, and beyond
• The methodologies and design frameworks you put in place will improve quality and productivity across future memory IP projects

What You'll Need

• 12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols
• Deep technical knowledge of at least one of HBM, DDR, LPDDR, or similar memory protocols, including controller architecture, training, and PHY interface
• Proven ability to define and execute complex digital architectures from concept through RTL implementation and silicon bring-up
• Strong understanding of AMBA or similar on-chip interconnect protocols and how memory controllers integrate into SoC architectures
• Experience with advanced digital design tools and methodologies, including synthesis, timing closure, and low-power design techniques
• Excellent communication skills, you can explain a complex architectural tradeoff to a product manager, a verification lead, and a customer engineer without losing clarity
• Experience with HBM3, DDR5, or LPDDR5X is a strong plus

Who You Are

• You can walk into a whiteboard session with incomplete requirements and walk out with a block diagram that the team can build from
• When an RTL review surfaces a potential issue, you do not defend the design, you ask the right questions and figure out if it is real
• You have a point of view on what good architecture looks like, and you are comfortable pushing back when a feature request does not make sense
• You think about verification complexity while you are designing, not after the RTL is done
• You are comfortable working across time zones with teams in the US, Europe, and Asia, and you know how to keep a distributed team aligned
• You do not need to be the one writing every line of RTL, but you can drop into the code and debug a corner case when it matters

The Team You’ll Be Part Of

You will join a dynamic and focused team advancing Synopsys' memory interface IP portfolio. The team works on HBM, DDR, and LPDDR digital core protocols, collaborating closely with PHY, verification, and product teams across global sites. You will be a key technical contributor to the architecture and execution of one of these memory protocols, helping define what the next generation of memory IP looks like. The team values technical depth, clear communication, and the ability to solve hard problems without perfect information.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.