Analog Staff Design Engineer

ON Semiconductor; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

ON Semiconductor in Bengaluru, India is seeking a Staff Analog Design Engineer in NEW PRODUCT DEVELOPMENT, Power Management to join our growing team. You will design and deliver analog IP blocks, perform block/IP level simulations, and guide layout engineers to ensure timely IP delivery.

You will collaborate with validation, product engineering and test teams to measure silicon performance and ensure robust power-management solutions across automotive, industrial and consumer applications.

Qualifications

• BS in Electrical Engineering with 8+ years experience, or MS with 7+ years.
• Strong knowledge of analog IC design and power management.
• Experience with IP/block design, verification and layout coordination.
• Proficient in Cadence Spectre and system-level simulations.
• Excellent communication and teamwork skills.
• Familiarity with SiC/GAN/LED/motor applications is a plus.

Responsibilities

• Design and develop an analog IP block from definition to IP delivery.
• Design and simulation at block/IP level and present results.
• Guide layout engineers and monitor IP block layout progress.
• Coordinate with validation, product engineering and test teams to measure silicon performance.
• Own outcomes of design, verification, implementation, and execution of power management IPs.
• Plan and execute work to align with full-chip schedule.

Skills

Analog IC design

IP design

Block design

Schematic simulation

Verification

Communication skills

Team collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Spectre

MATLAB

Simplis

Job description

OnSemi is seeking a Staff Analog design Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including LED drivers, SiC/MOS/IGBT/motor/GAN drivers, Switches and efuses for consumer, industrial and automotive applications. In this role, you will focus on the following

• Design and develop an analog IP block from definition to IP delivery
• Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.
• Work with and provide guidance to layout engg and monitors the progress of IP block layout
• Work with validation, product engineering and test engineering teams to enable them to measure Si performance
• Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops
• Able to plan and execute the work in timely manner aligning with full chip schedule.

Minimum Requirements

BS in Electrical Engineering or related +8 years of experience, or MS + 7 years of experience

Qualification

• Solid track record of delivering block/IP level design
• Understand and execute IP design, simulations methods, boundary conditions, stress and reliability simulations, PVT/PMC/SOA simulations.
• Good communication skills to make detailed technical presentations
• Good understanding of various building blocks like LDOs, gate drivers, comparators, linear regulators, gm-stages, charge pumps etc
• Experience in SiC/GAN/LED/Motor, Efuse and smart Switches etc is plus
• Strong Analog IC design skills, debug of complex silicon problems using simulations and/or bench testing
• Understanding of power transistor Design, Layout, and Robustness
• Experience in system tools such as Simplis or MATLAB for architectural simulations, Cadence Spectre for schematic capture, simulation
• Strong verbal and written communication skills
• Ability to quickly ramp on new systems and processes
• Demonstrated strong interpersonal, analytical and problem-solving skills
• Ability to work in teams

• Design and develop an analog IP block from definition to IP delivery
• Design and simulation at the block/IP level during execution phase, present the block results to review team in timely manner.
• Work with and provide guidance to layout engg and monitors the progress of IP block layout
• Work with validation, product engineering and test engineering teams to enable them to measure Si performance
• Own technical outcomes of design, verification, implementation, and execution of power management IPs with complexities that can span from simple regulators to complex mixed-signal designs and control loops
• Able to plan and execute the work in timely manner aligning with full chip schedule.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.