Analog Design Senior Manager - SerDes

Synopsys Inc; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Synopsys in Bengaluru seeks an experienced senior analog design lead to head a team delivering multi-Gbps SerDes IP in advanced FinFET and GAA nodes. You will continue hands-on schematic review and drive critical path optimization while mentoring engineers to build robust designs for PCIe and Ethernet connectivity.

The role requires 14+ years in analog design, 1-2 years in management, deep CMOS knowledge, and the ability to translate standards into concrete architectures.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or related field.
• 14+ years of hands-on analog design experience focused on high-speed SerDes
• 1-2 years in a management or supervisory role leading analog design teams
• Deep transistor-level circuit design expertise with CMOS fundamentals across SerDes sub-circuits
• Proven ability to design IP for PCIe and Ethernet high-speed connectivity
• Strong understanding of mixed-signal challenges including timing, layout effects, and reliability

Responsibilities

• Lead a team of analog designers developing multi-Gbps NRZ and PAM4 SerDes IP.
• Translate standards into block-level specifications and architectures.
• Review simulations, characterization data, and post-silicon findings; propose design updates.
• Build schedules and plans for complex IP development across nodes.
• Mentor team through hiring, coaching, and career growth conversations.
• Collaborate cross-functionally with digital, layout, and CAD teams to resolve integration challenges

Skills

Analog design

SerDes IP

CMOS fundamentals

Leadership

Team mentoring

Education

Bachelor's or Master's in Electronics Engineering

Job description

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over a decade building high-speed SerDes circuits that actually ship in products, not just pass simulations. The difference between a VCO that locks cleanly across PVT and one that drifts at the edge of spec is something you see coming three design reviews earlier, and you are the kind of engineer who catches it before it becomes a silicon problem. You think in both transistor-level trade-offs and team-level execution. When a junior designer brings you a sampler topology, you can spot the bandwidth bottleneck in two minutes and sketch three alternatives that might work better, then help them choose the right one for this particular standard and this particular process node.

Managing a team does not mean you stop designing. You still get into the schematics when a critical path needs attention, but you also know when to step back and let your team solve it. You care about building engineers, not just circuits. At Synopsys, you will lead a team developing multi-Gbps SerDes IP in advanced FinFET and GAA nodes, and the work you guide will power connectivity in systems that matter.

What You'll Be Doing

• Lead a team of analog designers developing multi-Gbps NRZ and PAM4 SerDes IP from standards analysis through silicon bring-up
• Conduct technical design reviews for critical SerDes sub-circuits including equalizers, samplers, voltage and current-mode drivers, serializers, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, and DACs
• Translate SerDes standards and system requirements into block‑level specifications and circuit architectures that your team can execute against
• Review simulation results, electrical characterization data, and post‑silicon debug findings, then recommend design updates or corrective actions
• Build project schedules and action plans that keep complex analog IP development on track across multiple process nodes
• Develop and mentor your team through hiring, technical coaching, design reviews, and career growth conversations
• Work cross‑functionally with digital designers, verification engineers, layout teams, and CAD to resolve mixed‑signal integration and timing challenges

The Impact You Will Have

• Deliver high-speed SerDes IP that enables PCIe and Ethernet connectivity in customer products across a range of industries
• Define circuit architectures and design strategies that set the technical direction for your team and influence IP roadmap decisions
• Improve design quality and reduce post‑silicon risk by catching issues early through structured reviews and hands‑on technical guidance
• Build a stronger analog design team by hiring well, coaching effectively, and creating an environment where engineers grow their skills
• Accelerate time to market by maintaining clear schedules, removing blockers, and keeping cross‑functional teams aligned
• Influence process node readiness and design‑for‑reliability practices through your team's work in advanced FinFET and GAA technologies
• Shape the technical standards and documentation that define how SerDes IP is designed, tested, and delivered at Synopsys

What You'll Need

• Bachelor's or Master's in Electronics Engineering or related field
• 14+ years of hands‑on analog design experience focused on high‑speed SerDes applications
• 1 to 2 years in a management or supervisory role leading analog design teams
• Deep transistor‑level circuit design expertise with strong CMOS fundamentals and experience across a wide range of SerDes sub‑circuits including receive equalizers, samplers, drivers, serializers, deserializers, VCOs, phase mixers, DLLs, PLLs, bandgap references, ADCs, and DACs
• Proven ability to design IP for high‑speed connectivity standards such as PCIe and Ethernet
• Solid understanding of mixed‑signal design challenges including analog‑digital interface timing, ESD circuit techniques and layout, custom digital design for high‑speed logic paths, and layout effects like matching, reliability, and proximity
• Experience with design‑for‑reliability considerations including electromigration, IR drop, and aging effects

Who You Are

• You stay technically hands‑on even in a management role. You can still open a schematic, debug a phase noise issue, or review a layout for matching and reliability concerns without losing a step.
• You know how to assess complex analog work quickly. When a designer brings you a PLL architecture or a driver topology, you can identify the risk areas and suggest a better path forward in one conversation.
• You build schedules that reflect reality, not wishful thinking. You understand what takes three weeks versus three days in analog design, and you plan accordingly.
• You communicate clearly with people who do not live in your domain. You can explain a jitter budget to a digital architect or a post‑silicon issue to a program manager without losing the technical thread.
• You care about growing your team. You give feedback that helps people get better, you create space for engineers to take on stretch work, and you hire people who will raise the bar.
• You push back when something does not make sense. If a spec is unrealistic or a timeline ignores a known process limitation, you say so and propose an alternative.

The Team You’ll Be Part Of

You will join a team focused on high-speed SerDes IP and transistor‑level analog and mixed‑signal design. The work supports high‑speed connectivity applications including PCIe and Ethernet. Your recruiter will share more about team size, reporting structure, and specific product roadmap responsibilities during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.