#22908-CoE -DE -DFT Engineer

Quality Ai

India

On-site

INR 1,200,000 - 2,400,000

Full time

9 days ago

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Job summary

QualityAI is seeking a DFT Engineer (CoE) in India to drive hierarchical DFT strategies including ATPG and scan design. You will verify scans at RTL and gate level, and prepare deliverables for silicon execution while collaborating with design and verification teams to ensure robust DFT coverage.

The role requires hands-on experience with ATPG methods, scan verification, and familiarity with Mentor Tessent; a Master’s degree is a plus for this position.

Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field or equivalent practical experience.
Experience with multiple DFT projects in scan design and verification.
Experience with DFT techniques, ASIC DFT synthesis, simulation and verification flow.
4 years of experience in ATPG methods.
Familiar with EDA tools like Mentor Tessent from Siemens. Master’s degree preferred.

Responsibilities

Develop DFT strategy for hierarchical DFT, scan, and ATPG.
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform scan verification at RTL and gate level.
Prepare scan content and deliverables for Silicon Engineering execution.
Debug scan patterns on tester per requirements.
Coordinate with Design, Verification, and Physical Design teams to meet DFT scan requirements.

Skills

DFT design

ATPG

Scan Design

DFT verification

ASIC DFT synthesis

silicon bring-up

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Equivalent practical experience

Master's degree in Electrical Engineering

Tools

Mentor Tessent

Job description

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#22908-CoE -DE -DFT Engineer

Date: 26 Sept 2026 Company: QualityAI Country/Region: IN Job responsibilities:Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvementsPerform scan verification at RTL and gate levelPrepare scan content and delivarables for Silicon Engineering executionDebug scan patterns on tester per requirementWork with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.Experience with multiple projects in DFT scan design and verification.Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.4 years of experience in Automatic Test Pattern Generation (ATPG) methods.Preferred qualifications:Familiar with EDA tools like mentor ( tessent) from Siemens . Master's degree in Electrical Engineering.Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).Experience in fault modeling.Experience in SoC cycles, including silicon bringup and silicon debug activities.Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of .silicon issues)

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