Principal Analog Layout Engineer

Chipright; Galway; On-site; EUR 70,000 - 90,000; Full time

Job summary

A semiconductor company seeks a Principal Analog Layout Engineer for its Galway facility. The ideal candidate should have over 5 years of experience, primarily with layouts of 65nm and below, and a strong understanding of timing circuits. Familiarity with Cadence tools is essential. This role offers an opportunity to work on cutting-edge technologies in a collaborative environment, contributing to advanced semiconductor products.

Qualifications

• Minimum 5 years experience but ideally >8+ years Experience.
• Experience in 65nm and below (ideally 22nm and below).
• Chip finishing experience is a bonus.

Responsibilities

• Design and review analog layouts.
• Ensure compliance with timing requirements.
• Collaborate with other engineers on critical paths.

Skills

5+ years of experience

Understanding of layout for critical timing

Experience with Cadence PVS/QRC/Pegasus

Job description

Principal Analog Layout Engineer, Galway

Client: Chipright

Location: Galway, Ireland

EU work permit required: Yes

Job Description:

Principal Analog Layout Engineer

• Minimum 5 years experience but ideally >8+ years Experience
• Experience in 65nm and below (ideally 22nm and below)
• Understanding of layout for critical timing (PLL, DLL, clock distribution)
• Understanding of matching techniques for timing circuits and current cells
• Chip finishing experience a bonus
• Experience with Cadence PVS/QRC/Pegasus